The problem with that is, you can't pour both sides independently, and then stitch them independently. Maybe if it's low density, so you have a lot of room for 'jumpers'? But with so much extra space, you're probably worse off due to stray inductance, which again, is proportional to length. Depends what.
So the result is, you still need a bypass cap per pin (more or less), to ensure good power quality.
You also get maximum distance (and therefore inductance) between planes, which is annoying on 1.6mm proto builds. You can get 1 or 0.8mm protos just as cheaply, which gets you practical trace widths for controlled impedances, and naturally, half the via/plane inductance; but the result is flimsier.
Keep in mind the one electromagnetic benefit of plane pairs: you can reduce the number of bypass caps in the design. Everything acts like one big connection. Planes are as ideal as we can get on a PCB. If you aren't doing it to save caps, it's not doing anything beyond the convenience of simply not having to route that net.
Also, if you're saying a point-to-point route isn't good enough, you are saying a 0.33 ohm (from my above example) supply impedance isn't good enough. How do you know? Does your logic require very stable supply (say 1% or less variation)? Does it exhibit step changes over 100mA? (Maybe -- 74AC shoot-though is about that bad, for all gates in a chip switching simultaneously.)
A step change of 100mA * 0.33 ohms = transient of about 33mV peak. Or worse, at resonant frequencies, if the network is poorly damped -- hence the importance of ESR damping. Without an intentional (or accidentally useful) bulk cap, expect a peak Q around 3-6, or a peak supply impedance up to 2 ohms. Still, if you need 1% ripple, and have much quieter gates of say 16mA peak draw (maybe typical of 74HC with a few gates switching simultaneously), you're set!
Justified by arguments like this, you might even consider increasing the distance between bypass caps in a linear-routed design. That is, bypassing every other load, for example. 74HC without strict timing requirements is fine like this. CD4000 you hardly need anything at all in the design, it's so slow. Or you might choose a star or multi-star arrangement, where the bypass cap is central to a group of loads. The trace length to each load might be an inch or two, but is that added 20nH really going to kill it? 5% drop is 8 A/us, or 20mA in 2.4ns. That's safe for 74HC!
The power supply is a network like any other, and subject to straightforward engineering design, like any other. There is no need to ignore it, to blindly say "we need a plane", or "we need a sea of bypass caps!" It can be analyzed very easily and roughly, as my above hand-waves show, or simulated in great detail for not much more trouble.
The one restriction on this type of analysis: it assumes independent traces, with no coupling. You can't get away with this analysis if there isn't a solid plane in the design. That's why stitching is critical. Coupling, or cross talk, can also be estimated, and it should only need to be considered for signal quality purposes. (If you're doing it to figure if there's a possible functional problem in the first place, or to check if it's okay to run this trace under the switching supply -- no, don't do that.)
Tim