FPGA - Debounce with Latch

[ElectricGuy]

HI;

I'm very new to FPGAs, so please, go easy on me!

I have a push button an FPGA and a LED.
I'm trying to code in VHDL a program to on the press of the switch, debounce it and lights up the led. When i press again, it switchs off the led, and so on;

At this moment i have the debounce part, but i really don't know how to get the latching part.

I'm coding in VHDL.

Any help?

CODE

Code: [Select]

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity teste is
  GENERIC(
    counter_size  :  INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)

    Port (   
  SELOPE    : in  STD_LOGIC;                                 
  OPERATION : out STD_LOGIC;                               
  CLOCK     : in  STD_LOGIC                           

);  
end test;

architecture Behavioral of test is
    SIGNAL flipflops   : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
  SIGNAL counter_set : STD_LOGIC;                    --sync reset to zero
  SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
 signal H: STD_LOGIC;             
begin

counter_set <= flipflops(0) xor flipflops(1);   --determine when to start/reset counter

process(CLOCK)
begin

    IF(CLOCK'EVENT and CLOCK = '1') THEN
      flipflops(0) <= SELOPE;
      flipflops(1) <= flipflops(0);
      If(counter_set = '1') THEN                  --reset counter because input is changing
        counter_out <= (OTHERS => '0');
      ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
        counter_out <= counter_out + 1;
      ELSE                                        --stable input time is met
        H <= flipflops(1);
      END IF;   
    END IF;
   end process;

    process(H)
      begin
OPERATION <= H;
end Behavioral;

Operation is the LED
SELOPE is the Switch

[marshallh]

http://www.fpga4fun.com/Debouncer2.html

[retrolefty]

HI;

I'm very new to FPGAs, so please, go easy on me!

I have a push button an FPGA and a LED.
I'm trying to code in VHDL a program to on the press of the switch, debounce it and lights up the led. When i press again, it switchs off the led, and so on;

At this moment i have the debounce part, but i really don't know how to get the latching part.

I'm coding in VHDL.

Any help?

 Never been exposed to VHDL, but latching/toggling is usually done with some kind of flip-flop element which acts as a memory function.

[ElectricGuy]

http://www.fpga4fun.com/Debouncer2.html

Thnka for the link, but i don't even know what is a MODULE. I'm just really starting

[ElectricGuy]

HI;

I'm very new to FPGAs, so please, go easy on me!

I have a push button an FPGA and a LED.
I'm trying to code in VHDL a program to on the press of the switch, debounce it and lights up the led. When i press again, it switchs off the led, and so on;

At this moment i have the debounce part, but i really don't know how to get the latching part.

I'm coding in VHDL.

Any help?

 Never been exposed to VHDL, but latching/toggling is usually done with some kind of flip-flop element which acts as a memory function.

Yes, but i'm having dificults implementing that in VHDL

[hamster_nz]

Debounce is hard to get right. It sounds easy but it is hard,

What do you really want?

Do you want low latency? (e.g. change at the quickest /shortest press).

Do you want press-and-hold to blink?

What time windows are you thinking for filtering the bouncing?

If you know what you really want it gets easier far easier to implement. If you don't know exactly what you want it will always seem wrong.

It also might pay to think of it as filtering noise out of a continuous stream of 0s and 1s from the switch.

...0000000010101010111010010101011111111111111111111110101010101000000000000...

needs to become:

...0000000000000000000011111111111111111111111111111111111111111111111100000...


The easy bit is toggle the LED on each 0-to-1 transition of the filtered signal.

The least-effort way is usually that the output signal and input signal must differ for 'n' cycles before the output state changes - something like this hack (which has not been checked or tested at all!)

Code: [Select]

      -- set the LED to the state of toggle.
     led <= toggle;

process(clk)
   begin
       if rising_edge(clk) then

           -- Toggle when output_state has changed from 0 to 1.
           if filtered = '1' and filtered_last = '0' then
               toggle <= not toggle;
           end if;

           -- remember the last output state so we can detect changes in output_state
           filtered_last <= filtered;

           if filtered = input_state then
               count <= count_max;
           else
              -- count down and change when count = 0
              if count = 0 then
                output_state = not output_state; -- flip output to other state.
                count <= count_max;
              else
                 count <= count-1;
              end if;
           end if;
       end if;
   end process;


[TerminalJack505]

My VHDL is really rusty but I think you are looking for something like this:

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Toggle is

    generic (
        POR_Q  : std_logic := '0' -- Reset value of Q.
    );

    port (
        -- Inputs...
        Clk : in std_logic;
        Rst : in std_logic; -- Asynchronous.

        -- Output...
        Q   : out std_logic
    );

end Toggle;

architecture Behavioral of Toggle is

    QOut : std_logic;

begin
   
    -- Toggle the output 'Q' each time a positive-going edge is seen on Clk.
    -- If Rst is asserted then 'Q' is set to POR_Q.
   
    process (Rst, Clk)
    begin

        if Rst = '1' then
            QOut := POR_Q;
        elsif rising_edge(Clk) then
            QOut := not QOut;
        end if;

        Q <= QOut;

    end process;

end Behavioral;


[ElectricGuy]

Hi TerminalJack505 and  hamster_nz;

My problem at this point its not debounce, its the latching part.

My code is working good for debounce, but it does not latch. The outupt of my debounce is;

Code: [Select]

H <= flipflops(1);

And then i you turn on the led

Code: [Select]

process(H)
      begin
OPERATION <= H;

But it only turns on when i press the button, and i want to latch the led, on press turns on, on press turns off.
I'm going insane, but like i said before, i'm really a beginner! 

[hamster_nz]

Hi TerminalJack505 and  hamster_nz;

My problem at this point its not debounce, its the latching part.

My code is working good for debounce, but it does not latch. The outupt of my debounce is;

Code: [Select]

H <= flipflops(1);

And then i you turn on the led

Code: [Select]

process(H)
      begin
OPERATION <= H;

But it only turns on when i press the button, and i want to latch the led, on press turns on, on press turns off.
I'm going insane, but like i said before, i'm really a beginner! 

With bad form:

Code: [Select]

led_toggle_proc: process(flipflops(1))
  begin
   if rising_edge(flipflops(1)) then
      led <= not led;
   end if;
end process;

with better form:

Code: [Select]

led_toggle_proc: process(clk)
  begin
   if rising_edge(clk) then
      if  flipflops(2) /= flipflops(1) then
          led <= not led;
      end if;
      flipflops(2) <= flipflops(1);
   end if;
end process;


[ElectricGuy]

It is working with the "Bad_Form", but still missing some press of thw button.
With the "better form" is acting worst, it looses even more press fot the button
Thank you hamster_nz

[that_guy]

Probably not your main bug but...

Code: [Select]

counter_size  :  INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)

19 bits at 50Mhz does equal 10.5ms however...

Code: [Select]

SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output

That's a 20-bit vector.

[ElectricGuy]

Probably not your main bug but...

Code: [Select]

counter_size  :  INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)

19 bits at 50Mhz does equal 10.5ms however...

Code: [Select]

SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output

That's a 20-bit vector.

Thank you that_guy, but its not that. i'm changing that several times to do the experiences and didn't update the code here.

[hamster_nz]

What's the latest code look like?

[tggzzz]

It would help the OP if he can start thinking in a way that will enable more complex finite state machine (FSM) designs to be easily expressed, implemented, debugged and modified.

This is a good short introduction to a simple flexible style: http://www.gaisler.com/doc/vhdl2proc.pdf

[ElectricGuy]

What's the latest code look like?

Hi hamster_nz;

I'm not on the computer right now, but i will post the latest code here tomorrow.
It is working, but not the best aproach for sure.

It would help the OP if he can start thinking in a way that will enable more complex finite state machine (FSM) designs to be easily expressed, implemented, debugged and modified.

This is a good short introduction to a simple flexible style: http://www.gaisler.com/doc/vhdl2proc.pdf

Yes, i know that, but honestly i don't know how to code an FSM in VHDL yet. Hope to get there.
I'm just beginning. Thanks for the link!

[tggzzz]

It would help the OP if he can start thinking in a way that will enable more complex finite state machine (FSM) designs to be easily expressed, implemented, debugged and modified.

This is a good short introduction to a simple flexible style: http://www.gaisler.com/doc/vhdl2proc.pdf

Yes, i know that, but honestly i don't know how to code an FSM in VHDL yet. Hope to get there.
I'm just beginning. Thanks for the link!

First learn how to think in terms of FSMs. From personal experience they are useful in many circumstances from hardware through to software running in distributed enterprise applications servers. Too many "softies" think FSM==compiler parsing, so you'll have an advantage over them.

Secondly read and understand examples.

Thirdly, don't be put off - interesting and worthwhile things always take a while to master.