Author Topic: FPGA I/O Problems  (Read 11996 times)

0 Members and 1 Guest are viewing this topic.

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
FPGA I/O Problems
« on: July 04, 2014, 06:18:17 pm »
Hello, I've been wanting into FPGA programming so purchased one from ebay; link below (probably not the best choice but I'm on a budget).

http://i.ebayimg.com/t/FPGA-Cyclone-Altera-FPGA-EP1C3T144-Learning-Board-USB-Blaster-JTAG-Programmier-/00/s/MTI4M1gxNjAw/z/7OUAAOxydB1ShiOP/$_35.JPG

I have the most basic of knowledge of Altera and Quartus programs having programmed a simple state machine for a school project. So I thought implementing a simple AND/OR circuit would be simple, but for the life of me I can't get the I/O pins to work.

I know it's being programmed because I've tried using the on-board LEDs but they are being powered, instead of being set ground. So it got programmed it just didn't work properly. Then I tried making a simple AND circuit that would turn on a LED through a transistor on a breadboard; that's when I found the I/O pins weren't working. I've gone through assignment editor on Quartus to make sure everything was enabled but no luck. Could it be the board just doesn't work or maybe something else I've misses?

I would appriciete any help. Thanks. 

Here is the link to the datasheet the vendor provided:
https://skydrive.live.com/redir?resid=CB363E5D4717263F!145&authkey=!ALM9biha4hcIStw
It's in the folder A153-datasheet.

 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #1 on: July 04, 2014, 06:50:35 pm »
Any way you can make the datasheet available other than in a place that needs live credentials?
For example zip it or if it's a pdf just attach it here (under "attachments and other options" when you post.
A zip file of your project will be helpful as well as a picture showing the pin you are using and the breadboard.
 

Offline theatrus

  • Frequent Contributor
  • **
  • Posts: 352
  • Country: us
Re: FPGA I/O Problems
« Reply #2 on: July 04, 2014, 07:05:51 pm »
FPGA I/O pins have a lot of options (LVDS, etc). Which did you pick?
Software by day, hardware by night; blueAcro.com
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #3 on: July 04, 2014, 08:11:59 pm »
Of course, I'll attach them all.

I've used,
PIN_7: LVDS2n/DQ1L3
PIN_120: VREF0B2
PIN_121: LVDS2n
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #4 on: July 04, 2014, 08:38:00 pm »
You are using 3.3 LVTTL default which is fine for all inputs and outputs.

On the pin planner you are using PIN_7 as your output like you described, but the purple wire is hooked to PIN_121, so you might want to change the pin planner to use PIN_121 as the output.

Edit: U5 and U6 are the dip switches had to look for a high res image of your board on the internet. Let me revise what I said:

As for inputs to the and gate you have them hooked to PIN_39 AND PIN_40 on the U5 header but I can't see the wires for the inputs to the AND gate. Edit, this makes sense now since they are the dip switches 1 and 2 of U5.

So they should be on (towards the board) to make PIN_121 be on, on the dip switch closer to the red reset button I think.



Maybe you can first use the switches PIN_60 and PIN_61 (pulled high) as the inputs to the and gate, and if both switches are on, the led should turn on.

Edit: Also the schematic seems to be missing one of the switches bank, and it's hard to tell where those other headers are at without looking at the bottom of the board.


Edit: also it's hard to ascertain the ground from the FPGA to the board, it would be using the common house ground maybe.
You could probably hook the ground pin from header U6 (make sure you get the right side ones since the other side are connected to the FPGA) and have it as common ground, but without the full circuit that is feeding the LED is hard to see what is going on.

Maybe you can power the circuit from the FPGAs 3.3V and GND on U5 (3.3V on even pins) and U6 (GND on even pins) lower right of schematic you attached. Not sure where those headers (6x2 each) are located in the board.
Not sure where your board has access to 3.3V and GND those U5 and U6 are the dip switches and confused me just by looking at the very spartan schematic
« Last Edit: July 04, 2014, 09:02:47 pm by miguelvp »
 

Offline theatrus

  • Frequent Contributor
  • **
  • Posts: 352
  • Country: us
Re: FPGA I/O Problems
« Reply #5 on: July 04, 2014, 08:49:22 pm »

Of course, I'll attach them all.

I've used,
PIN_7: LVDS2n/DQ1L3
PIN_120: VREF0B2
PIN_121: LVDS2n

If you set it to LVDS that's a problem. Thats a current mode, 100ohm differential signal. Great for high speed, terrible for lighting up some LEDs :)

Switch it to a TTL or CMOS logic type input and output.
Software by day, hardware by night; blueAcro.com
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #6 on: July 04, 2014, 08:53:59 pm »

Of course, I'll attach them all.

I've used,
PIN_7: LVDS2n/DQ1L3
PIN_120: VREF0B2
PIN_121: LVDS2n

If you set it to LVDS that's a problem. Thats a current mode, 100ohm differential signal. Great for high speed, terrible for lighting up some LEDs :)

Switch it to a TTL or CMOS logic type input and output.

That's the name of the pin, the pin planner shows them as default 3.3V TTL levels
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #7 on: July 04, 2014, 09:09:55 pm »
So I think it's the ground path.

the power pins and ground on your board are on the lower right of this picture, I don't know about the other headers because there is really not a good manual for your board and I can't see the silk screen of the bottom.

 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #8 on: July 04, 2014, 09:26:27 pm »
Going out to a BBQ, 4 of July and all that, I hope you get it working, I'll check later tonight.
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #9 on: July 05, 2014, 05:17:33 am »
OK, currently I have the output set to PIN_120. I found that there's voltage across 120 and any other header pin, about 3.3v. Is that how it's suppose to be?

I connected PIN_121 to ground on the breadboard and LED lit up, but it does so regardless of the AND inputs; which are the dip switches 1 and 2 for U5.   
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #10 on: July 05, 2014, 05:38:02 am »
The problem is not that your purple wire doesn't have the voltage needed, but there is no common ground between the FPGA and your circuit.

You have to connect the FPGA ground wire to your circuit ground so that the signal works instead of just being floating.

The ground pin I believe is the third one on the lower right header next to the k1 push button. It should be labeled GND.

Alternate to that you can power your breadboard with the voltage pins on the lower right, not sure what your LED circuit needs but you have 3.3V and 5V on your FPGA pins.

pin 121 is an i/o port you should not ground that.

Edit: To be more clear.
Quote
OK, currently I have the output set to PIN_120. I found that there's voltage across 120 and any other header pin, about 3.3v. Is that how it's suppose to be?

No, the 3.3v should be between your output pin and the ground of the FPGA. The problem you have is that the breadboard circuit and the FPGA don't have a common ground.

« Last Edit: July 05, 2014, 05:57:07 am by miguelvp »
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #11 on: July 05, 2014, 06:19:56 am »
OH ok yes I understand you.

I set it up so the circuit is powered and grounded exclusivity by the board, but the problem persists of PIN_120 not responding to the inputs.
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #12 on: July 05, 2014, 06:44:50 am »
Seems like now it's wired right.

One thing is that FPGAs don't retain the programming unless the board supports start up flashing of the FPGA, I can't tell if yours does or not.
When you unplug and plug the FPGA does it always have all the LEDs and 7 segment display on? if that is the case you might need to reprogram it.

Seems like all your unused pins are high, and your program doesn't talk to the LEDs or the 7 segment display so it's strange that they are lit up.

I usually have my unused pins set as input tri-state. you can get to that in: Assignments->Device click on the "Device and pin options" around the middle top right of the pop-up window, select "unused pins" and set them to "as input tri-state".

One thing you can do too if you have a multimeter is to measure the voltage without being connected to the breadboard circuit to see if your output signal has the right value compared to ground when flipping the switches. If it does, then the problem is on the breadboard circuit.

I usually check the outputs before connecting them to a circuit if I'm unsure what I'm doing. DMM for circuits like yours or a scope for other signals that change over time. Once I'm satisfied with the outputs I will connect it to the circuit.
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #13 on: July 05, 2014, 07:31:08 am »
Yes very haha

Mine does not, I have program it every time I turn it on.
When I first turn it on the LEDs are off, the 7 segment display is on but displays 4s instead of 8s.

I measured the voltage of the output, without being connected to the board, and it runs high regardless of the switches.
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #14 on: July 05, 2014, 07:37:15 am »
Hmm,

can you program a single not gate from dip switch one PIN_40 i believe (the lower left one next to the red button) to connect to the output pin? so if off it should turn the output pin to 3.3V and if on it should turn the output pin to 0V
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #15 on: July 05, 2014, 08:31:03 am »
It stays at 0v whether the switch is on or off.
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #16 on: July 05, 2014, 08:36:39 am »
That is very odd, you sure you are flipping the right switch? try them all on and all off. (edit both dip switches)

And by odd I mean that the actual logic is there since the not is actually making the output 0V where before it was always 3.3V so it's not the FPGA

Edit: If no change try the K1 button PIN_67 as the input.
« Last Edit: July 05, 2014, 08:41:22 am by miguelvp »
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #17 on: July 05, 2014, 09:12:43 am »
Yeah I've been trying them all this whole time.

Ok well that worked. When the button is unpressed output is 0v and when pressed output is 3.3v
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #18 on: July 05, 2014, 08:14:29 pm »
Yeah I've been trying them all this whole time.

Ok well that worked. When the button is unpressed output is 0v and when pressed output is 3.3v

So when the button is unpressed the input pin is pulled high to 3.3V with a 10K resistor. Then the Not gate switches it to 0V on the output.
You can put the AND gate and attach the inputs to K1 and K2 so the LED will only be lit if both buttons are not pushed. Push either one or both and the LED should go off.

you can put a NOT gate on each input before going to the AND gate so that the LED only lights up when both buttons are pushed.

This is the schematic part of your buttons:


The DE0-Nano dip switch is wired like your buttons are:


Now your first dip switch is wired to bring the pin to 3.3 when closed or floating when open. I'm not sure what this does since they don't show any other resistor or ground connection.

The other dip switch grounds the pin when closed, or leaves the pin floating when open.
Schematic:


If the pins are pulled high somewhere else (not shown in the schematic) maybe you will have more luck with the other set of switches in U6 PIN_54 and PIN_53, that will force the pins to ground when closed. You can start with just the NOT test on PIN_54 to see if it toggles between 0 and 3.3V

I don't understand if the U5 dip switch is supposed to be pulled low to ground and not shown on the schematic and U6 dip is supposed to be pulled high (like the buttons) but not shown on the schematic either. So both set of switches might be useless unless they have un-populated resistors under them somehow.

Edit: on top of all that there are two other connectors with pull high and the other with 3.3V/GND and a pin.
I wished I knew Chinese to translate all of the blocks on the schematic. But I hope they have something to do with the dip switches ground or 3.3V connections.




« Last Edit: July 05, 2014, 08:26:09 pm by miguelvp »
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #19 on: July 06, 2014, 12:18:09 am »
Edit: on top of all that there are two other connectors with pull high and the other with 3.3V/GND and a pin.
I wished I knew Chinese to translate all of the blocks on the schematic. But I hope they have something to do with the dip switches ground or 3.3V connections.



The left one is a temperature sensor connector:
http://www.nciku.com/search/zh/detail/%E6%B8%A9%E5%BA%A6%E4%BC%A0%E6%84%9F%E5%99%A8/211187

The right one is an infrared receiver connector:
http://www.nciku.com/search/zh/detail/%E7%BA%A2%E5%A4%96%E6%8E%A5%E6%94%B6%E6%9C%BA/577434

So nothing to do with the dip switches, going to try to translate the dip switches next by drawing them on that site

drawing the characters only revealed that they are in fact 2 dip switches :)

« Last Edit: July 06, 2014, 12:37:28 am by miguelvp »
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #20 on: July 06, 2014, 01:31:43 am »
Maybe one of the pin i/o configurations will help with the floating signals. I don't know much about that so I'll leave here some documents in case one of them has information on how to setup an I/O pin to distinguish between a floating pin and a 3.3V input, or a floating vs a ground input.

http://www.altera.com/support/devices/io/features/io-features.html
http://www.altera.com/literature/hb/qts/qts_qii52013.pdf

Did your board come with any examples that use those dip switches?
 

Offline marshallh

  • Supporter
  • ****
  • Posts: 1462
  • Country: us
    • retroactive
Re: FPGA I/O Problems
« Reply #21 on: July 06, 2014, 05:11:24 pm »
Dumb question: Are you recompiling after changing the pins?
Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #22 on: July 06, 2014, 06:57:59 pm »
@miguelvp:
I tried the U6 dip switches and they work just like the K1-K4 buttons. Haha great you found a way to translate it, I was trying to get a hold of a friend for that.
I've looked through some of those documents before but I'll do it again just to make sure. 

Also came with chip data and experimental codes.

@marshallh: Yes
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #23 on: July 06, 2014, 07:01:23 pm »
It won't let me reply with the attached files  :-\
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #24 on: July 06, 2014, 07:08:13 pm »
Needs to be a zip file or tar and no bigger than 1Meg the list of the allowed extensions is listed in the attachment.

So you put a project that uses U5 no need for the rest to figure out how U5 is supposed to work.
BTW, if they do have samples that use the U5 dip switch do they work?
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #25 on: July 06, 2014, 07:45:54 pm »
You mean project using U6?

They have samples, Idk how to open it though.
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #26 on: July 06, 2014, 07:48:07 pm »
Well, you got U6 working, I was wondering if there is a project that uses U5 (the one that you can't make it work  and always puts 3.3V regardless of the switch position).
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #27 on: July 06, 2014, 07:56:37 pm »
I would have liked to use the U5 switches but as long as I place a NOT in front of the U6 and the buttons, it works just as well.

And thank you for all the help, I definitely appreciate it  :D
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #28 on: July 06, 2014, 08:45:43 pm »
You are welcome.

That example you attached is in VHDL and uses the buttons to display 1, 2, 3,4 on the first digit of the 7 segment display
So if you press K1 it displays 1, K2 2, etc.

The pins are assigned left to right so the binary order as they wired it is:
Dot,G,F,E,D,C,B,A  and they are active (on) when low (0) so a 1 in the assignment turns the segment off.

  -A-
F    B
 -G-
E   C
  -D- (Dot)

Edit, clearer picture:


Code: [Select]
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECL7S  is
PORT ( key_data  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
       LED7S      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       LED7 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  ) ;
end DECL7S ;
 
 ARCHITECTURE behav OF DECL7S IS
 signal led_temp: std_logic_vector(3 downto 0);
 BEGIN
  PROCESS( key_data )
  BEGIN
     LED7S <="00000000" ;
     led_temp<= key_data ;
  CASE  led_temp  IS
   WHEN "1110" =>  LED7 <= "11111001";    --  1
   WHEN "1101" =>  LED7 <= "10100100";    --  2
   WHEN "1011" =>  LED7 <= "10110000";    --  3
   WHEN "0111" =>  LED7 <= "10011001";    --  4
   WHEN OTHERS =>  NULL ;
   END CASE ;
  END PROCESS ;
 END behav;

To open it you open the qpf file as a project I usually avoid using spaces in the project path so I did remove the spaces Testfile/ButtonsandLEDB.
Also, I noticed that LED7S  is defined as 8 bits (7 downto 0) but that is the digit selector and it's supossed to be just 4 bits (3 downto 0)

Edit: and if you make the change to 4 bits then this:
LED7S <="00000000" ;
should be changed to this:
LED7S <="0000" ;
Or quartus will complain about it.
« Last Edit: July 06, 2014, 09:09:04 pm by miguelvp »
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5550
  • Country: us
Re: FPGA I/O Problems
« Reply #29 on: July 06, 2014, 09:04:41 pm »
And if you want to learn more past using schematics and jump into VHDL or Verilog or SystemVerilog Altera has a great (and Free) curriculum

http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html
 

Offline mlugo2Topic starter

  • Contributor
  • Posts: 24
  • Country: us
Re: FPGA I/O Problems
« Reply #30 on: July 07, 2014, 11:52:57 pm »
Thanks! I think I'll look around their samples, maybe I'll find some that use the U5 dip switches.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf