FPGA SDR SDRAM control for frame buffering

[Axk]

Please correct me if I'm wrong.

I'm thinking about buffering frames coming from a 30fps camera module (640x480) in SDR SDRAM to match this to a 60fps VGA output.

In my understanding with this specific task it should be fairly straightforward to write an SDR SDRAM controller in Verilog (they call it a static controller in this presentation: http://www.es.ele.tue.nl/premadona/files/akesson01.pdf).

With its 64 ms refresh interval the DRAM won't need explicit refreshing because at 30fps each row in the utilized area of the DRAM will be read from or written to at least each 33 ms (I'm thinking of a double buffer one part written to while the other is read from and then they switch roles).
I could interleave writes with reads with internal SRAM FIFO buffering to make up for the gaps in the reads and writes and gaps because of changes of rows.

[Axk]

So I can confirm that a primitive controller (without refresh even) for SDR SDRAM for a frame buffer is relatively straightforward.
What was not easy is to debug the whole chain of Verilog modules: camera -> FIFO -> Sdram -> FIFO -> VGA considering SDRAM is not a dual port memory.
There is even a good Verilog model of the Micron SDR SDRAM I used (MT48LC8M16A2) which makes testbenching the whole RTL design much easier.