Have I gone mad?

[king.oslo]

Hello there,

Until now I was certain this was true:

P-channel MOSFET conducts when the voltage at the gate is more negative than the threshold voltage relative to the source.
N-channel MOSFET conducts when the voltage at the gate is more positive than the threshold voltage relative to the source.

Is this true?

I am sorry to ask such a fundamental question, but LTspice seems to be suggesting I am wrong (see the attachment). If the above was true, I would expected the green voltage to switch between 172V and 0V @ 25% duty cycle.

Thanks.M


EDIT: What I actually want is the 172V at 75% duty cycle!

[IanB]

I have only a sketchy knowledge of FETs, but I wonder, shouldn't we consider source in one case and drain in the other?

[amspire]

You have two source followers which are non-inverting and a bit less then unity gain,  it is working as it should.

My thinking is a relay may be the easiest solution particularly if you can arrange for it to switch off when the regulator falls below 14V, or the voltage before the regulator drops to less then 17V. The reason I like a relay is the relay can short out the voltage across the divider, so there is zero volts - a second contact can switch off the 172V as well.

An alternative suggestion is to use a 3 position 2 pole make-before-break switch for an off-standby-on switch.  In the off mode,the input power is off and the divider is shorted. In the standby mode, the input mains is on, bit the divider is still shorted.  In the on mode, then mains is on, and the divider is unshorted. Becuae you have to switch through the standby position, it ensures the power up-power down sequence is correct.

Richard.

Edit: what I think you intended was the P-channel mosfet with a 10K resistor gate to source. Then a N-channel mosfet or NPN transistor with a 180K resistor between the drain/collector and the gate of the p-channel mosfet. Source/emitter to 0v. You then add a simple zener circuit to turn the n-channel/npn on when the voltage of the regulator is over 12V.

[Kremmen]

Hello there,

Until now I was certain this was true:

P-channel MOSFET conducts when the voltage at the gate is more negative than the threshold voltage relative to the source.
N-channel MOSFET conducts when the voltage at the gate is more positive than the threshold voltage relative to the source.

Is this true?

I am sorry to ask such a fundamental question, but LTspice seems to be suggesting I am wrong (see the attachment). If the above was true, I would expected the green voltage to switch between 172V and 0V @ 25% duty cycle.

Thanks.M

For starters, there are N channel and P channel devices and both come in 2 kinds: the enhancement mode and the depletion mode transfer characteristic. So you have 4 fundamentally different kinds of MOSFET. I took the liberty of attaching a picture from the 3rd ed. of Physics of Semiconductor Devices by Sze and Kwok, hopefully fair use covers this. If not i will of course remove it. Perhaps that picture clarifies the differences.

Then, your circuit simply has the problem that halfway through you switch the common reference potential from source - to source +. This can be done but it has pitfalls and your circuit falls into one of them. M1 contols the gate of M2 in phase with the clock pulse, switching it between - and circa 11 volts or so. Actually you don't really need the fet because the clock source already does the same thing. Now for M2 the reference (node where the source pin is connected) is the + pole of the voltage source. So nominally the source voltage is 0 and the drain voltage is -172 V. This would be the way to orient a P channel fet voltages. Now the idea of this circuit is that M1 produces voltages alternating between 0V and some -15 V to the gate of M2, in M2 reference orientation above. Unfortunately this is not what happens in practice. M1 only swings some 11V above its own reference which is the -172 V rail in M2 reference frame. In M2 reference it is between -161 and -172 volts. So the "output" (i.e. M2 source) swings just enough to maintain the fet in a conducting state, the voltage keeping a constant difference to that applied on the gate.
You can confirm this by checking the M2 gate voltage in LTspice. You will see that it keeps a constant voltage difference against M2 source. Every time the pulse source and M1 switch, there will be a current spike in M2 gate circuit as the charge rebalances due to the change in source voltage.
This circuit can easily be modified to do what you want. Just take M2 gate voltage from M1 drain and switch the resistor from M1 source to its drain. The output phase of course changes around but that sould not be a major issue.

[Psi]

Hm.. This is something i wasn't aware of, and probably should have been.

Learn something everyday i guess.

[ejeffrey]

You will probably never see a depletion mode MOSFET.  All jfets are depletion mode because an enhancement mode jfet would require forward biasing the junction.  Of course, discrete jfets are not that common these days either.

[king.oslo]

You will probably never see a depletion mode MOSFET.

Why? Are they not useful?M

[king.oslo]

Richard, I had no success with your suggestion I attached a screenshot to show what I did.

PS Richard: I thought I would use this circuit to instantly empty the caps on the 100V reference whenever the supply for the chopper opamp is off, so that I get no voltage @ power on and no latched up. I have had a few 170V shocks whilst prototyping because I forgot the stored energy in the caps. This will sort me out, right?


Kremmen, your suggestion worked as I expected, thanks, however, I made the mistake to write that I want the 172V square wave to have duty cycle 25%. What I really want is the square wave at 75%.

That can be done with a single n-ch depletion transistor, or two n-ch enhancement trasistors, right?

I am trying to find a depletion mode nmos on farnell. How do I search for it? Is that an nmos with a negative V_GS?

And thanks for the diagram of the fets. Excellent stuff.M

[amspire]

Those spice results are perfect. It is working, except for the fact you have shorted the p-channel to 0v, instead of connecting it to a 22K resistor. I assumed you wanted the p-channel to be a switch before the 22K resistor. Perhaps your idea was something different.

Richard.

[SeanB]

Too complex. Lose the resistors and M2, and if the pulse polarity is wrong then use a single CMOS gate as an inverter, driven from the 15v supply.

If all you want is to discharge the capacitors what is wrong with a bleed resistor? If you want fast discharge use a power rail of lower voltage and place a relay across it, with the bleed resistor connected to the NC contact.

Depletion mode transistors are both rare and low voltage RF devices. Add to that expensive and easy to blow up.

[king.oslo]

Perhaps your idea was something different.

Yes, I probably have to work on my communication. As months have passed, I have learnt to trust you knowledge of electronics, Richard. Thanks for taking the time to help me

Too complex. Lose the resistors and M2, and if the pulse polarity is wrong then use a single CMOS gate as an inverter, driven from the 15v supply.

If all you want is to discharge the capacitors what is wrong with a bleed resistor? If you want fast discharge use a power rail of lower voltage and place a relay across it, with the bleed resistor connected to the NC contact.

Thanks SeanB. Cannot do the bleed resistors. It will screw up the circuit. Perhaps I can do as you suggested or use two NFETs.

[SeanB]

A relay would be easiest, i am looking at a tiny EBD26/2-28 relay in a board here, a tiny ( size of a 8 pin cerdip on edge) relay rated for 115V0.5A with DPDT contacts, and a 28V coil. Sits in a sandwich made from 5 PCB's bolted together.

[king.oslo]

A relay would be easiest, i am looking at a tiny EBD26/2-28 relay in a board here, a tiny ( size of a 8 pin cerdip on edge) relay rated for 115V0.5A with DPDT contacts, and a 28V coil. Sits in a sandwich made from 5 PCB's bolted together.

Sounds tiny Sean, but the problem is that I have solid state fetish 

Check out the attachment. For the sake of learning: As you can see, the voltage drops to 3V at drain of M2, not 0V. Is this because because the M2-resistance is too high?

[SeanB]

Move R1 to the other side of R2 and rerun the sim.........

[king.oslo]

SeanB, you are right.

But dang, this doesn't work. I am loosing current through R1 when the 172V rail is high. This will screw up accuracy.M

[SeanB]

Make R1 1M or more, and add a resistor of 10% of that value across the drive transistor. With a Mosfet you can go very high in value, provided you use a device so that the gate capacitance is not too much of a low pass filter at the frequency that you are switching, and you are prepared to live with the slow switching ( relative to the nanosecond you achieve with a low impedance drive) and slightly increased dissipation. As you will probably be using a high voltage device select one with a low maximum current ( reduces size of die and thus capacitance) and the highest voltage you can get easily in a TO220 housing ( will easily handle the switching power without a heatsink needing to be added other than either mounting vertically or bolting to a pad on the board). That will reduce bleed current, and not make the edges too slow.

[king.oslo]

Make R1 1M or more, and add a resistor of 10% of that value across the drive transistor. With a Mosfet you can go very high in value, provided you use a device so that the gate capacitance is not too much of a low pass filter at the frequency that you are switching, and you are prepared to live with the slow switching ( relative to the nanosecond you achieve with a low impedance drive) and slightly increased dissipation. As you will probably be using a high voltage device select one with a low maximum current ( reduces size of die and thus capacitance) and the highest voltage you can get easily in a TO220 housing ( will easily handle the switching power without a heatsink needing to be added other than either mounting vertically or bolting to a pad on the board). That will reduce bleed current, and not make the edges too slow.

The problem with this circuit is that it draws some current through the resistors whilst the power on.M

[SeanB]

Then the power for the first unit will have to come from another rail, with a voltage of between 10 and 20V using a 10k or so resistor. 15V will ensure the mosfet turns on fully, but a lower voltage will work if the device is above the threshold voltage at that gate voltage, at the expense of having a higher on resistance and a temperature dependance.

[amspire]

I just went back and looked at the circuit that need the changes to stop the latchup:
https://www.eevblog.com/forum/projects-designs-and-technical-stuff/100vdc-reference-circuit/msg96357/#msg96357

The problem with any electronic switch to short out the output capacitor is that the capacitor needs to be shorted before there is any voltage - and as the voltage first starts to rise, there is no voltage to turn this switch on.

So my solution is to use the circuit I suggested as a switch before the 22K resistor, and I would remove the output capacitor - it should work totally fine without it, and removing the capacitor means that when the ouput voltage is switched off, then there is no energy strage device left past the switch, so nothing to cause latchup.

So I would take this circuit:

https://www.eevblog.com/forum/beginners/have-i-gone-mad/?action=dlattach;attach=23764

I would open up the drain of M2 and remove the 1K R2. I would then use this circuit as a switch before the 22K resistor with the M2 source going to 172V and the drain going to the 22K.  This now means the 172V has to be switched ON rather then a short switched off.

A side reason why I would remove the output capacitor is that the 1K resistor was added for stability - to add a zero on the output to guarantee a high stability. The trouble is that with the 1K, any leakage in a capacitor directly on the output will cause an error, and since it is not needed, it may as well go.

Richard.

[king.oslo]

The problem with any electronic switch to short out the output capacitor is that the capacitor needs to be shorted before there is any voltage - and as the voltage first starts to rise, there is no voltage to turn this switch on.

I do not think this will be a problem. The 170V rail comes from a seperate transformer than the +-15V rails.

I would open up the drain of M2 and remove the 1K R2. I would then use this circuit as a switch before the 22K resistor with the M2 source going to 172V and the drain going to the 22K.  This now means the 172V has to be switched ON rather then a short switched off.

You are advising me to:

- lose the output cap. OK.
- Not to drain the capacitors when the power switches off, rather blocking the output from the caps so that the voltage cannot reach the opamp? Did I understand correctly?

M

[amspire]

Yes, you have understood. Add a 1 M ohm resistor across the 172 v to discharge the capacitors when the power is off.

Richard.

[free_electron]

Here is another piece of information about mosfets that few people realize..

a N channel conducts of the Gate is more positive than the channel.
a P channel conducts of the Gate is more negative than the channel.

There is no such thing as 'drain and source'. How the current flows to through the channel is irellevant. we use the name of drain to denote the pin the current flows into and source for the pin the current flows out of. but they can switch places ! the mosfet does not care.

in chip design both are just a terminal.
in classic three pin devices the source is the pin where the substrate ( the bulk)  is connected ( a mosfet is a 4 terminal device. ) this bulk connection gives you a free diode ( called the intrinsic diode) across drain and source.

In harddisks we use mosfets in this fashion to create the drive voltage for the dsa. Instead of using a simple boost converter with an inductor and forward diode we put a mosfet. whenever the diode would conduct we actually turn on the mosfet. so we don't suffer 0.6 volts loss across the bulk diode. ( in step downs this is called synchronous rectification , in boost converters you can do the same). Once the coil is discharged we turn off the mosfet and the bulk diode is reverse plarized so it blocks the higher voltage from returning. During a controlled powerdown we actually turn on the mosfet again so the current can now flow the other way and is correctly discharged. The mosfets don't care at all.

[amspire]

There is no such thing as 'drain and source'. How the current flows to through the channel is irellevant. we use the name of drain to denote the pin the current flows into and source for the pin the current flows out of. but they can switch places ! the mosfet does not care.

What you say is true except that mosfets with separate substrate connections are now so rare, they have to be treated as a special exception. This mean the idea of drain and source is useful in that the source on almost every mosfet is internally shorted to the substrate. A pity really, as you can do some interesting things with a separate substrate  connection.

You are right though in that it is really worth remembering that when the mosfet turns on, it conduct currents in both directions. For less then 0.6V source-drain voltage, you can more or less swap the source and drain. There are advantages in turning the mosfet on to conduct reverse currents instead of relying on the substrate diode - lower voltage drop, and no stored charge in the diode junction to slow the mosfet switching speed down.

Richard.

[vxp036000]

Only true in CMOS, and even then not always. This is generally not true at all for discrete FETs.  Reverse the source and drain on an RF power FET and watch what happens to the gain (if the device doesn't smoke, that is).  Substantially different doping profiles are used for the source and drain of a FET to maximize performance.  Reversing source and drain on a FET is just as bad as reversing the collector and emitter on a BJT.

Here is another piece of information about mosfets that few people realize..

a N channel conducts of the Gate is more positive than the channel.
a P channel conducts of the Gate is more negative than the channel.

There is no such thing as 'drain and source'. How the current flows to through the channel is irellevant. we use the name of drain to denote the pin the current flows into and source for the pin the current flows out of. but they can switch places ! the mosfet does not care.

in chip design both are just a terminal.
in classic three pin devices the source is the pin where the substrate ( the bulk)  is connected ( a mosfet is a 4 terminal device. ) this bulk connection gives you a free diode ( called the intrinsic diode) across drain and source.

In harddisks we use mosfets in this fashion to create the drive voltage for the dsa. Instead of using a simple boost converter with an inductor and forward diode we put a mosfet. whenever the diode would conduct we actually turn on the mosfet. so we don't suffer 0.6 volts loss across the bulk diode. ( in step downs this is called synchronous rectification , in boost converters you can do the same). Once the coil is discharged we turn off the mosfet and the bulk diode is reverse plarized so it blocks the higher voltage from returning. During a controlled powerdown we actually turn on the mosfet again so the current can now flow the other way and is correctly discharged. The mosfets don't care at all.

[SeanB]

The only commonly available device with separate source is the humble 4007 6 FET unit, where you get 4 devices with separate source and drain connections for playing around with. Of course limited to 15V and 5mA like most CMOS gates.

[vxp036000]

In a device physics class, we actually calculated the effect on transconductance of switching the source and drain on a power FET.  The device went from an amplifier to a very inefficient attenuator.  The gm was laughable.  And this wasn't even taking into account the effect of the bulk diode tied to the source. 

[amspire]

In a device physics class, we actually calculated the effect on transconductance of switching the source and drain on a power FET.  The device went from an amplifier to a very inefficient attenuator.  The gm was laughable.  And this wasn't even taking into account the effect of the bulk diode tied to the source.

Not sure I understand this statement at all.  However inefficient, the current gain is still close enough to infinite for most purposes, and voltage gain doesn't matter since you know you need 3-10V on the gate, but you are limited to 0-0.6V reverse voltage on the output since there is the substrate diode. I think if you are using the mosfet in the reverse direction, voltage gain is unlikely to be a concern.

Overall, the DC power gain in the reverse direction is massive.

Are you talking about AC properties at some frequency?

Richard.

[vxp036000]

The transconductance will be much lower with the source and drain interchanged.  That is, a much larger change in input voltage is required to produce the same change in output current.  And yes, I am referring to an amplifier, not a DC circuit. 

I can't really think of a legitimate reason for reversing the source and drain in a DC circuit, though.  This is, from the manufacturers perspective, an unspecified operating condition.  I haven't seen manufacturers publish reverse bias data on FETs.

[TerminalJack505]

The transconductance will be much lower with the source and drain interchanged.  That is, a much larger change in input voltage is required to produce the same change in output current.  And yes, I am referring to an amplifier, not a DC circuit. 

I can't really think of a legitimate reason for reversing the source and drain in a DC circuit, though.  This is, from the manufacturers perspective, an unspecified operating condition.  I haven't seen manufacturers publish reverse bias data on FETs.

Here's an interesting example of when reversing source and drain comes in handy.



This is from the LTC4412 datasheet.  Both of the P-channel MOSFETs are 'backwards.'  The LTC4412 relies on the body diode upon startup to power itself.  (Vin and Sense are both power supply pins.)  Once powered-up it will switch on the appropriate FET.

[vxp036000]

Clever.  I learned something new :-)  I'll admit that I haven't worked much with DC circuits, aside from simple amplifier biasing schemes.  Do they recommend a particular FET for which reverse bias operation is specified?

[amspire]

The transconductance will be much lower with the source and drain interchanged.  That is, a much larger change in input voltage is required to produce the same change in output current.  And yes, I am referring to an amplifier, not a DC circuit. 

I can't really think of a legitimate reason for reversing the source and drain in a DC circuit, though.  This is, from the manufacturers perspective, an unspecified operating condition.  I haven't seen manufacturers publish reverse bias data on FETs.

It is extremely useful in synchronous rectifiers to eliminate the power wastage of the 0.7V diode drop. In buck converters that use a mosfet to replace the schottky diode to the 0v rail, this mosfet is switched on and is conducting in the reverse direction every time the main switching  mosfet to the + supply switches off.

Also it is used all the time in Mosfet-based solid state relays.



Richard.

[SeanB]

Add to that the major use, of which the SSR is just a specialist portion, being used in analogue switches.

Just about any mosfet can be used in this application, the exceptions being those with built in intelligence, either an overtemp shutdown or overvoltage/overcurrent protected ones. Any with a monitor output ( other than a current sense via a portion of the die being split out for this) are most likely not going to work well, mostly due to the parasitic diodes built into the monitoring systems.

[TerminalJack505]

Clever.  I learned something new :-)  I'll admit that I haven't worked much with DC circuits, aside from simple amplifier biasing schemes.  Do they recommend a particular FET for which reverse bias operation is specified?

The datasheet has a section called "External P-Channel MOSFET Transistor Selection."  It actually doesn't mention anything specific with regards to reverse bias operation.  This is for power switching so maybe power MOSFETs are more symmetrical so far as source/drain goes?  Or, maybe the reverse biasing is less of an issue since the FET will be operated in the linear region?

[free_electron]

extremely usefull in synchronous rectification.

the mosfet as a 4 terminal device ( only accessible to people who design chips ) has no distinction between drain and source. this is why you can use them to conduct ac signals . that's how an 4066 4051 4052 4053 dg40x does it. simple mos between in and out. apply charge on the gate and off you go.

the principles governing mosfets are very simple. like charges repel, dislike charges attract. the channel is a resistive connection with two end terminals. on top of this is an isolation barrier followed by a piece of metal. this is essentially a capacitor. the channel being one plate the gate metal being the other plate and the oxide forming the dielectricum. To have a charge on a capacitor you need a voltage delta.

charge also implies 'dislike'. you cant have a 'charge' if both plates have the same level.
So , for an enhancement mode mosfet : if you apply a voltage delta across the gate capacitor ( gate sits at different potential than the channel ) you create a charge there. You have the plates at a different level , the tunnel opens (because the other plate of the gate capacitor has the opposite charge of the one i put on the gate...

hmm let me rephrase that.
n-channel enhancement mode mosfet : there are not enough electrons in the channel to conduct end to end ( electrons are negative charge carriers )
by placing a positive charge on the gate capacitor ( i pull my electrically connected plate more positive above the plate attached to the channel ) i create electrons in the channel ( i attract them there. my terminal is positive. so the other one needs be negative and electrons are 'negative' carriers. now there are enough electrons in the channel and current can flow end to end.

same with a pmos enhancement. not enough 'holes' by default. by pulling one plate of the gate capacitor negative ( applying electrons there ) i attract holes on the other plate. this creates an electrical pathway end to end in the channel.

depletion mosfets have an abundance by default ( we shoot them in during production in the doping process . this is done with an ion implanter. ) so there you need to push the charge carriers ( whether electrons or 'holes') away so they stop the conduction path in the channel.

this is why you don't see a lot of depletion mosfets: they are not very practical... lets say you want to make an inverter. this is normally done by making a totem pole of a pmos and an nmos. at powerup none of these conducts... put depletion mosfets there and you have a big fat short circuit at powerup... not very usefull. they are used in chips (where something must be 'on' by default) and for some very specialistic applications. i know two or three depletion mosses that are available as 3 pin devices.

now, a mos is a 4 pin device. there is also an electrode formed by the piece of material it is constructed in. we can't leave that floating.. because it forms another capacitor that may get charged ..... and the mos could turn on and never be turned off. so we tie this 'bulk' ( sometimes also called substrate ) to one end of the channel. Because there is a parasitic diode between bulk and channel , we now denote drain and source so people know how the parasite sits. this diode is not very good in the sense of power handling. for real power mosfets we( i always say 'we' because i work in this field. i design silicon ) actually put an extra diode on the same die and shunt it across drain-source.

here's a few tidbits of 'fun' info.

the construction of a mos is governed by length and width of the gate. make a longer gate and more electrons can cross in parallel : more current. make a wider gate and it can hold more 'pressure' : voltage when not conducting. What is width x length? : the plate size of a capacitor.
larger plates : more capacitance... that's why big fat powermosses that have large standoff voltage have higher capacitance than tiny mosfets... the plates are larger. increase current handling : capacitance goes up ( length changes ) , increase voltage blocking and capacitance goes up ( gate widens )

in the 'old days' a cmos designer would mark down how long and wide he wanted a gate to be. there was no selective implantation like today and to make a mosfet have a better channel ( lower resistance ) they needed to make it wider ( longer gate = wider channel they lay 90 degrees rotated). if you go to Intel's website and go to the museum section you can download the full schematics of the 4004 processor. they have for each transistor marked in pencil how long and wide the gate needed be.

layers were grown uniform so only length and width came into play. now we have selective implantation and we can control 'depth' ( it is actually the cross section of the channel under the gate that determines the current handling capability. for a fixed layer thickness would play with the width. with selective implantation you make the layer locally thicker.

MOSFEt : metal-oxide-semiconductor field effect transistor.
field effect i have described above : attract and repel charge on the channel.
metal oxide semiconductor denotes the construction. you have a semiconductor ( the channel ) an oxide ( the dielectricum ) and a metal ( the gate 'plate' ). for a long time there was no metal' involved. the oxide is actually conductive in the order of a few megaohms. the actual isolator is a thin barrier where the channel meets the oxide. so they were using the oxide as routing. since all you care about is 'charge' the high resistivity of the gate electrode did not matter. problem is you create an r-c filter. the c being the gate capacitor , the 'r' being the resistance of the  oxide. this bogs down how fast you can go ... for linear you don't care, for switching you do. you want to go from off to on as fast as possible. any state in-between is wasted energy.

so only later did they cover the gate oxide with metal to get charge in there quickly.

if you charge the gate capacitor you can put the mosfet away for years. pick it back up and it will still be in the state you put it in ( provided nothing discharged the gate capacitor like an esd bag or humidity ). you can do the test with an ohmmeter. measure between drain and source, put finger on gate. it will conduct. take ohmmeter away. come back tomorrow and measure again drain-source. it will still conduct.

eproms and eeproms use a floating gate. they are essentially momosfets. metal oxide metal oxide.
in discharged state that piece of metal internally does nothing. charge is attracted and 'hops' the first barrier and lands on the internal piece of metal. now the situation changes. you all of a sudden have two charged capacitors in series... that middle , floating piece, has trapped charge. remember the experiment with the ohmmeter and finger ? bingo. that's how you store it ...
you do need high voltage and you do a little bit of damage every time you make charge 'hop' across the isolating barrier ( this hopping is called tunneling : look up fowler-nordheim tunneling for the physics ). so that's why eprom and eeprom cells do wear out...

the gate of a mosfet is light sensitive. so by making the top oxide permeable to light (UV light ) you can actually discharge that floating piece of metal... and you get an uv erasable eprom. fun fact : placing charge on the gate writes '0'. that is why eproms read FF when empty ...
no charge : channel not conducting. the mos sits between ground and read line. place charge : mos turns on so read line becomes low : 0.


now all of the above is just the basics. you can play with geometries , making one end of the channel thicker than the other , different shapes of gates ( hexagons ) and this creates additional properties. some are good for switching , some good for analog some good for RF.
Finfets, Hexfets, you name it.. now we have 3d fets where the gate materiel not just lies on top but all around the channel ( as a torus around the pipe ). so these pinch off even better and faster. as opposed to stupid silicondioxide we now use hafnium based materials ( so called high-K ) because we can make much thinner dielectrics that still will still isolate well and hold charge well ( a half charged fet conducts in the ohmic region.. not good for power dissipation in the system)

when 'frying' a fet you most commonly blow a hole in the gate isolator.. you no longer have a capacitor there and it's game over ...

i could go on and on ...