Another schematic that I can't wrap my head around

[Evy]

I can see that this is a three stage amplifier. The CPCC is the output stage. I have not yet stumbled upon the variant where there resistors R₄ and R₅ in between the two "complementary" transistors.

Shouldn't the output from the second stage (the PNP transistor in this case) be "inserted" between the two diodes like below? I am not sure how the signal passes from the 2nd stage to the 3rd. Please help me 



Also I cant seem to find the "load", could perhaps R₅ be the load?

[Benta]

Very nasty class-B output stage with lots of crossover distortion. Do not copy at home 

[Gyro]

In both diagrams, the diodes are kept forward biased:

- In the bottom diagram by the resistors to +ve and -ve rails,
- in the top diagram by R3 and T2. T2 is acting as an emitter follower from the first stage differential pair.

As long as the two diodes are kept forward biased, they are just acting as a voltage source, compensating the the Vbe's of the two output transistors, so it doesn't matter where the signal is input.

Edit: R4 and R5 are low value resistors normally <1R to provide some emitter degeneration and improve linearity.

[T3sl4co1l]

The load is to be placed at \$v_o\$.

The PNP is a current source, so two things are true:
1. It supplies bias, in place of the top resistor in your second diagram.
2. Because the diodes have a very low impedance when forward biased (the dynamic resistance of a diode goes as \$\frac{V_{TH}}{I_f}\$ (where Vth ~= 26mV), they act as a supernode (not quite, but close).  That is: any change in current (AC), connected to any terminal of any diode, will have a very similar effect on the circuit.

To illustrate this more clearly, leave off the transistors and concentrate on the bias network (PNP or top resistor, two diodes, and R3 or bottom resistor).  (This is reasonable because base current is small compared to the current flowing in this path.)  The dynamic resistance of the diodes might be 10 ohms each, while the resistors might be 1k or more.  The AC voltage drop across the diodes, in response to an AC input current on any node, is small, no matter which node it's applied to.

So you could very well use the second circuit, with the PNP connected to the tap, as shown.  But this has an odd effect:

The PNP carries DC bias current, so the diode currents will not be equal.  This isn't a problem as long as the difference is small -- but then your output voltage range will be small, because the PNP can only pull up so far over that range.  (Think about the V = I*R change in the resistors.)

So the top resistor just makes things worse.  Why not remove it, right?

That doubles the Thevenin resistance loading down the node -- that is, for a given input current \$\Delta i\$, you get twice the \$\Delta v\$.  That's a win.  But then the top diode isn't biased.  So, let's just move the PNP up there, so its bias current goes in, and... et voila, we have the top circuit!

Tim

[Gyro]

Damn, didn't notice it was a PNP (clearly not an emitter follower)

[Evy]

But what if I wanted to calculate "maximum allowed bias current in the second amplifying stage if B_f = 50 and maximum current delivered to the load is 400mA". How would I do that?

Should I perhaps assume that there is an imaginary load sitting between v_o and ground?

[T3sl4co1l]

Maximum current is had under short circuit conditions.

That would be holding Vo constant, i.e., a load of zero ohms (and some DC bias so it doesn't just short everything out).

Beta-limited design is a poor way to go, but as a design example I guess that's okay.  It's a textbook question; textbooks have ideal (constant-beta) transistors.

Tim

[Evy]

Thank you for your reply! What should I short circuit? 

[Evy]

I am not sure what you mean by "short circuit conditions" should I short circuit an element?

[Zero999]

I am not sure what you mean by "short circuit conditions" should I short circuit an element?

Maximum current will exist when the emitter of one of the output transistors is held at a constant voltage, whilst one of the transistors is driven on as hard as possible. Consider what would happen if V_O is held at 0V and T2 is turned fully off or as hard on as is allowed by the PNP current source. Can you estimate the currents in R5 and R6?