Help to translate jitter design constraint in a frequency synthesizer design

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Hello to all,

I'm trying to design a frequency synthesizer with the old-school 4046 and 4017 ICs, with a scaling factor N = 1,5,7,10.

The input signal is a square wave with adjustable frequency from 1 kHz to 10 kHz.

I want to get a time jitter < 1% of the period.

I'm a newbie in PLL design, so I've done the only possible thing: study. I already knew control theory, filters, loop gain, stabilty and so on but I still can't understand where to start in the design to achieve the desired performance. Many books state that the design should start from the closed-loop bandwidth, but how do I relate this to jitter? I've read about calculating RMS time jitter from phase noise, but the datasheet of the 4046 has no data about VCO phase noise (for example) and I have zero infos about the source phase noise (the project is for college and the professor didn't give me any other information).

Please if you could help me, I literally have zero ideas on how to go on.

Thank you in advance.