Help with a Cascading BJT Amplifier <--- The Conclusion!!!

[cvriv]

This was a project given to me in class. Despite all my efforts... Im just not understanding this. I do to an extent, but I'm definitely missing something here. I attached the assignment and what i've done so far.

Im trying to solve the output impedance (Zo) for the first stage. I know and understand is that the output is impedance is usually low and input impedance is usually high. I understand that. I just dont know how to calculate the output impedance. My class book doesnt say anything about calculating it for a CE amplifer. Its says how to calculate it for a CC amplifier, but not a CE. The book uses zalues of output impedance all over the place to teach how the amplifers work but doesnt say how to calculate it. Also, the book doesnt teach anything about cascading BJT amplifiers as well. It uses a cascading BJT amplifier to teach about coupling and bypass amplifiers, but thats it! This is crazy. I google this and couldnt find anything that helps. I need to know how to calculate Zout and Av. The book says Av = rc/r'e; rc = RC||RL. Im pretty sure the input impedance of the second stage is the load resistance of the first stage correct? Please help.

[Ammar]

You should really be using Spice instead of Multisim, but it's not my uni course. The picture you have drawn with stage #1 and #2 is unfortunately incorrect. Start by drawing the AC small signal model. This means all capacitors are simplified to a short circuit and the 10V supply rail is connected to ground.

[Z80]

For a CE amplifier at low frequencies, the output impedance is determined by the collector resistor so there is nothing to calculate.  You can prove this to yourself either in the simulation or by building the circuit.  Inject a sinewave into the amplifier and measure the output voltage with the output open circuit (ensure the output doesn't clip).  Next connect a resistor across the output with the same value as the collector resistor, the voltage should now be half the open circuit value hence Zo = Rload = Rc.

[orolo]

When learning this, I liked Professor Najmabadi's notes on discrete amplifiers very much. This one covers what you need, page 6-26 contains an useful summary.

Output impedance of the first stage will be dominated by R3, as for your textbook.

The loaded voltage gain is -Rout / R4, with Rout = R3 || RL as above. Don't forget the minus sign.

There are some deviations from the ideal that don't count in your circuit. When computing output impedance, if R3 and RL were too big, you should take into consideration r0, the output impedance of the transistor (in the high tens to hundreds of kohms, typically). Also, when computing voltage gain, you must make sure that the emitter input resistance re is much smaller than R4. Since your collector current is about 1mA, re = 26 ohm, so re << R4, and you are safe.

Edit:

The source impedance of the second stage is the output impedance of the first stage. The input impedance of the second stage depends only on that stage: it's a combination of the bias divider impedance and the transistor imput impedance, with the former the dominant one. Just read the notes linked above, or some similar text, and it all will become clear.

[cvriv]

Is this the correct AC equivalent?

[orolo]

It is, more or less, correct. But note that the emitter resistors R4 and R8 do not appear in that AC equivalent, though they play a big role. Also, you should substitute each transistor in the schematic by its small signal equivalent: a base resistor in series with a collector current source, both shunted by the emitter.

Edit: Ops, forget about R4 and R8, I didn't notice they are bypassed by capacitors. Just use small signal model for BJT and you are ready to go.

[cvriv]

It is, more or less, correct. But note that the emitter resistors R4 and R8 do not appear in that AC equivalent, though they play a big role. Also, you should substitute each transistor in the schematic by its small signal equivalent: a base resistor in series with a collector current source, both shunted by the emitter.

Edit: Ops, forget about R4 and R8, I didn't notice they are bypassed by capacitors. Just use small signal model for BJT and you are ready to go.

Yes, R4 and R8 (the emitter resistors) are bypassed by the capacitors. Now... is the input impedance of the second stage the load resistance for the first? I have to calculate rE = RE || RL for the first stage so I can use it to calculate Av = rE / r'e + rE. What is the RL for the first stage? I think its the input impedance. Not sure though.

You said the source resistance of the second stage is the output impedance of the first stage. The source resistance of the second stage is what? The input impedance of the second stage?

Thanks for your help. I went to the college today to talk with the professor, but he wasn't there. Just my luck.

[Dan Moos]

Lets see if I can help.

You can sort of make a simplistic definition that the output impedance of a circuit is how much resistance the current has to get through to exit the stage. Input impedance is how much resistance it has to get through to enter it. Again, simplistic definition, but it intuitively describes things, wh8ich will make the following easier to grasp.

Ok, first the output impedance of a common collector BJT stage. Consider the path of the current exiting the stage. It starts at the voltage supply, and goes through the collector resistor. After that point, it has a fork in the road. Some goes through the transistor, and some goes to the next stage. Now here's the key part that answers your question. The resistance of the transistor is huge compared to that of any properly chosen collector resistor. With resistances, if two are vastly different, you can almost ignore the larger one if they are in parallel.  Say you have a voltage with two resistors in parallel to ground. One is 1k, and one is 1 meg. If you do the math, it will be basically be like the 1 meg resistor isn't even there. A similar relationship exists between the collector resistor, and the resistance of the transistor itself at that node. For all practical purposes, its as if only the collector resistor is there, because it is vastly smaller. Thus, in a normal common emitter BJT stage, the collector resistor is pretty much the output resistance.

Now, there is a finite, and calculate-able collector resistance of a transistor in a given circuit. Look into that if you like. The true  output resistance will be that in parallel with the collector resistor. You will usually find that the number doesn't change much.

Ok, for the input resistance. This is a bit dicey because it depends on the current gain of the transistor, which isn't exactly knowable.  Due to manufacturing limitations, the current gain of specific individual transistors of even the same type can be wildly different. You will learn how to design circuits that don't depend on this variable in time I'm sure, but for this discussion, just realize that the current gain of a transistor isn't a reliable number at all.

BUT, lets initially pretend it is. The input resistance of a common emitter BJT stage is basically the emitter resistor multiplied by the current gain of the transistor. So lets say your transistor has a current gain of 100. Lets also say your emitter resistor is 1k. 100*1k is 100k. That is what the input resistance will be. If you have any resistor from base to ground (often is), that resistance will be in parallel with your calculated resistance, and will change the numbers a little.

We can intuitively look at why the current gain of the transistor multiplies things. lets say you have 5 volts at the base, a 100ohm resistor at the emitter, and a transistor with a current gain of 100.

Since you have one diode drop from base to emitter, the voltage at the top of the emitter resistor will be 5v - .6 v = 4.4 volts. so, as expected, 4.4 volts across a 100 ohm resister is 4.4/100 = 44 mA. Since our 5 volts comes from the base, one would think that the current is coming from there too. But in our example if you were to measure the base current, you'd find that only 440 microamps was flowing. 1/100th what you expect. But how come there is a full 44 mA going through the emitter resistor? Where is the rest coming from? The collector current! That's how the transistor amplifies!

Ok, so from the base, only 440 micro amps is flowing with a voltage of 4.4v. What size resistor would flow 440 uA with 4.4 volts across it? 4.4/.00044 = 10k. So its as if the emitter resistor was 10k, rather than 100 ohms. Its exactly 100 times more. Its the current gain times the actual resistor!

Ok, o how does this effect your real world circuit. Well, lets pretend your first stage has a 10k collector resistor. We can call the output resistance (the source resistance in our example) 10 k. Ok, lets say sent th signal from there int the one we just described with the calculated input resistance of 10k.  Lets say our AC signal is 2v peak to peak. The 10k output impedance of the first stage forms a voltage divider with the 10k input impedance of the following stage. 10k/(10k+10k) = .5.  .5 * 2v = 1v. Our signal gets cut in half, just by linking these two stages! Its clearly a big deal, and needs to be a big part of design strategy. Later, when you learn about FETs, you will appreciate their input resistance properties compared to BJTs in this light.

Hope this helps. Others reading can feel free to correct any errors, as I typed this in a hurry.

[T3sl4co1l]

You should really be using Spice instead of Multisim,

Multisim is based on XSPICE.

Tim

[orolo]

 First, you need to know the DC quiescent operation point of the transistors. Assume all caps are open circuits. Then Q1 and Q2 are biased exactly the same, so you only have to work this out for Q1, and Q2 is identical. If Q1 is active, its Vbe should be around 0.6 volts, and it should minimally load the R1/R2 voltage divider. From the divider, the DC voltage at the base is 1.75 volts. Then the emitter voltage is 0.6 volts below, 1.15 volts. But then the across R4 flows a current of 1.15mA. So the collector current of Q1 is about 1.15mA, and then for the given beta, the base current is 7.18uA.

The base current is essential for the small signal behaviour of the amplifier. As you know from the Ebers-Moll transistor model, from base to emitter there is a forward biased diode. The small signal ac resistance of a diode is r_pi = Vt / I, where I is the DC diode current, and Vt the thermal voltage, about 26mV at room temp. So, for our transistor, the small signal base resistance is r_pi =  26e-3 / 7.18e-6 = 3.6K. This is the input resistance of the transistor, looking from the base.

So now you can rewrite your ac equivalent circuit as in the image attached below. The ac model of the transistor takes into account the resistance of the base, and the fact that the current across the base is amplified 160 times at the collector. So, for example, at the first stage the input voltage vs generates a current vs/3600 at the base. This is amplified to a current of vs/22.5 at the collector. Now, since that current flows through the parallel resistance of RC1, R11, R22 and 3.6K, you can derive the ac voltage at the collector. This is the amplification factor after the first stage. Doing just the same, you'll get the amplification after the second stage.

I hope this helps.

[cvriv]

First, you need to know the DC quiescent operation point of the transistors. Assume all caps are open circuits. Then Q1 and Q2 are biased exactly the same, so you only have to work this out for Q1, and Q2 is identical. If Q1 is active, its Vbe should be around 0.6 volts, and it should minimally load the R1/R2 voltage divider. From the divider, the DC voltage at the base is 1.75 volts. Then the emitter voltage is 0.6 volts below, 1.15 volts. But then the across R4 flows a current of 1.15mA. So the collector current of Q1 is about 1.15mA, and then for the given beta, the base current is 7.18uA.

The base current is essential for the small signal behaviour of the amplifier. As you know from the Ebers-Moll transistor model, from base to emitter there is a forward biased diode. The small signal ac resistance of a diode is r_pi = Vt / I, where I is the DC diode current, and Vt the thermal voltage, about 26mV at room temp. So, for our transistor, the small signal base resistance is r_pi =  26e-3 / 7.18e-6 = 3.6K. This is the input resistance of the transistor, looking from the base.

So now you can rewrite your ac equivalent circuit as in the image attached below. The ac model of the transistor takes into account the resistance of the base, and the fact that the current across the base is amplified 160 times at the collector. So, for example, at the first stage the input voltage vs generates a current vs/3600 at the base. This is amplified to a current of vs/22.5 at the collector. Now, since that current flows through the parallel resistance of RC1, R11, R22 and 3.6K, you can derive the ac voltage at the collector. This is the amplification factor after the first stage. Doing just the same, you'll get the amplification after the second stage.

I hope this helps.

I understand a lot of what everyone is saying. I just can't seem to pull it all together in my head. I'm going to get some sleep and then read what you wrote here try again. In my book, for a common-emitter amplifier it says that AV = rC/r'e; rC = RC||RL; r'e = 25mV/IE. Now this is a cascaded CE amplifier... could I use that AV formula for this circuit? What would the load resistance be though? I thought it would be the input impedance of the second stage but I dont think it is.

[salbayeng]

You are on the right track, just need to let it rattle around in your head for a while.

AV = rC/r'e; rC = RC||RL; r'e = 25mV/IE.

is all you need.

(1) You need to be  able  to get your head around how the gain is Rc/Re , it's basically because the same current flows through both, but keep drawing little pictures until it is second nature.  You should just look at a circuit, see 10k on top 1k under and know the gain is 10.

(2) start from the right half of Q2, there is an internal emitter resistor of "roughly 30ohms per mA" according to Bob Pease, (this allows for some ohmic resistance etc) any way 1ma >> Re =30.  In real life C4 has some ESR possibly 2 to 4 ohms .
So lets call Re = 30     so gain of second stage is 4700/30 = Av= 160

(3) look at left side of Q2, input impedance is hFE * Re ,  so 160 x 30 = 4800   , that is  the load resistance looking into the transistor,  there's some bias resistors shunting that, let's say ~ 3k  all up, this is again shunted by R1 so 1.8k all up , so Q1 Collector is looking at 1.8k

(4) look at right half of Q1 ,  current ~ 1mA , so Re about 30   so gain obviously  1.8k/30 = Av = 60

(5) look at left half of Q1 , Zin = hFE * Re = 4.8k   , add the shunt effect of the bias , Zin=3k.

(6) So total gain of 60 x 160

So that's got all the potatoes on your plate, now for some gravy.
Quickly eyeball where the poles and zeros are , on the input 1uF + 3k = 50Hz low freq rolloff pole,  and the same for second stage. The emitter bypass cap will also produce a low freq pole at 30 + 10uF = 500Hz, and a zero at  1k + 10uF = 1.6Hz  (the same poles and zeros at both emitters) , so an obvious improvement to the circuit would be to make C2 and C4 ~ 100uF (which is a typical bypass value). While all parts have parasitic inductances , it is only that present in C2 and C4 that will have any effect (because this is the lowest impedance node, so the lowest frequency to show up) this will show as an odd wrinkle around 5MHz, and the gain will drop off rapidly above that.
When you run the sim expect to see the poles and zeros in the above places.

When you do the simulation,  also add the parasitics for C2 and C4 ,  call it an ESR of ~4ohms and inductance of 10nH  (if in doubt about parasitic inductance, just eyeball the part and allow 1nH per mm of length).  Try re-running the sim with different parasitics to see the effect, noting that after 10years of operation the ESR of your caps may have doubled. Also when you build a circuit in the lab , try the low and high freq operation,  and square wave response, the more you poke it, the more you learn. (I built a nearly identical amp 40years ago, and then we had to run spice on a  teletype, and the plots would just be asterisks all over the page, my circuit performed better than the sim, I happened to jag some bypass caps with just the right parasitics to stretch the bandwidth.)

Do a time domain sim with a trapezoidal wave ~ 1kHz with ~ 100nS risetime , why is the output not the same shape,  what components (&poles and zeros) are responsible?.

Always remember that the hFE is highly variable, not just part to part, but can drop significantly at low temperatures,  with low Vce and with high Ic.
The capacitance value also drops markedly at low temperature.

[cvriv]

(1) You need to be  able  to get your head around how the gain is Rc/Re , it's basically because the same current flows through both, but keep drawing little pictures until it is second nature.  You should just look at a circuit, see 10k on top 1k under and know the gain is 10.

I'm aware that current flowing through the collector is the same current flowing the the emitter with the addition of the current flowing through the base, so the emitter current is slightly more than the collector current and a lot more than the base current. Just to be clear... when you say 10k on top and 1k under you mean Rc = RC||RL = 10k and r'e = 25mV\ IE = 1k? Right? That I understand as well. It's more easily understood with a single stage CE amplifier though. 

(2) start from the right half of Q2, there is an internal emitter resistor of "roughly 30ohms per mA" according to Bob Pease, (this allows for some ohmic resistance etc) any way 1ma >> Re =30.  In real life C4 has some ESR possibly 2 to 4 ohms .
So lets call Re = 30     so gain of second stage is 4700/30 = Av= 160

By internal emitter resistor you mean r'e? If so I calculated r'e = 25mV/1.05mA = 23.8ohms. You have rC as 4.7k because RC of the second stage is in parallel with an open right?. So i got 4.7k/23.8 = 197. That's a big difference. I find it interesting that your AV is the same as the hFE, because they are two different things right? One being voltage gain and the other being DC current gain.

(3) look at left side of Q2, input impedance is hFE * Re ,  so 160 x 30 = 4800   , that is  the load resistance looking into the transistor,  there's some bias resistors shunting that, let's say ~ 3k  all up, this is again shunted by R1 so 1.8k all up , so Q1 Collector is looking at 1.8k

You're losing me a bit here. By input impedance you mean the base input impedance? I got Zin(base) = 23.8*160 = 3.81k and an input impedance of Zin = R1 || R2 || Zin(base) = 2.61k. Is this right? My numbers are a lot different from what you are showing me. I am still able to follow along with you though. I'm doing everything the way the book shows and how my professor explained.

(4) look at right half of Q1 ,  current ~ 1mA , so Re about 30   so gain obviously  1.8k/30 = Av = 60

So why 1.8k/30? What about the 4.7k collector resistor of Q1? You said 1.8k was the load resistance looking into Q2. I would think that it would be rC = RC || RL = 4.7k || 1.8k = 1.3k. I got rC = 4.7k || 2.61k = 1.68k and Av = 1.68k/23.8 = 71.

(5) look at left half of Q1 , Zin = hFE * Re = 4.8k   , add the shunt effect of the bias , Zin=3k.

Again, I got a Zin(base) = 3.81k and a Zin = 2.61k.

(6) So total gain of 60 x 160

So by what you have here, the AV is 9600. I simulated the circuit and got a AV = Vout/ Vin = 23.2mVpk / 141uVpk = 164. I got total gain of 71 * 197 = 13987. LOL. This can't be right. I'm just going to hand in what I have now and that's it. I don't have anymore time right now to spend on this right now.

[orolo]

So by what you have here, the AV is 9600. I simulated the circuit and got a AV = Vout/ Vin = 23.2mVpk / 141uVpk = 164. I got total gain of 71 * 197 = 13987. LOL. This can't be right. I'm just going to hand in what I have now and that's it. I don't have anymore time right now to spend on this right now.

salbayeng is pretty right, and you too. My own calculations (as per my previous post) gave me a gain of about 12000, very similar to yours. The problem with fully bypassing the emitter resistor is that the final gain is very dependent on the transistor characteristics. For fun, I simulated your circuit with LTSpice, using two 2n3904 models, the standard model, and another model from an audio author called Cordell. The standard model (which is rather ideal) gave me a gain of about 12000. The Cordell model, which is more realistic, gave me a gain below 9600.

To compensate for manufacturer variations, it is good to include some emitter degeneration, then the feedback makes the circuit very predictable, at the cost of reduced gain. That's the reason I assumed at first that your circuit did not have the emitter resistors bypassed: as a first class exercise, the bypassing makes the analysis a bit harder. I had to look twice to make sure.

Edit:

Spice simulation, and small signal gain. The Cordell model gives a gain of about 79.25dB, that is 9172, while the standard models give about 81.67dB, that is, 12120. This for the same circuit, at the same temp, with the "same" transistors. I included in both circuits a series resistance of 4 Ohm, and a series inductance of 10nH, in the caps. It has little effect.

Edit 2:

In your simulation, make sure the input signal has a frequency high enough to not be attenuated by the implicit RC filters in the amplifier. I'd suggest 10kHz, basing myself on the spice results.

[cvriv]

Really? I got a gain of 164 in my simulation?!?!? I'm not doing something right here. Av = Vout/Vin right? I'm pretty sure Vin is 100uVrms via the source signal. I'm measuring 23.2mVpk via the virtual oscilloscope, which is about 16.4mVrms, so 16.4mV/100uV = 164. What did you do to get 12000 via your sim?

I attached a screen shot of my simulation and results.

[orolo]

Try a signal at 10 kHz, and 10uV amplitude. 60Hz is attenuated (look at the plots above) to about 42-45 dB, which is right what you get. The caps along with the input impedance of the amplifiers are RC filtering your low frequency input.

[cvriv]

Try a signal at 10 kHz, and 10uV amplitude. 60Hz is attenuated (look at the plots above) to about 42-45 dB, which is right what you get. The caps along with the input impedance of the amplifiers are RC filtering your low frequency input.

LOL. That's interesting considering my professor didn't specify a frequency for this circuit! I already changed the frequency to something higher prior to posting here and saw that the gain was huge. Do you find it weird that my professor expected me to calculate all that without a frequency? I guess you would have to know where we are in class to answer that. I find it weird. He misses stuff all the time so I'm assuming he left out information here.

[orolo]

Well, since the amplifier is AC coupled, it doesn't amplify DC. Av(DC) = 0. At high frequencies, it doesn't amplify because parasitics in the transistors and caps, the Miller effect, and all that. So Av(HF) = 0. At some band between DC and HF there is a sweet spot where the simplified small signal analysis is right, and you get the full amplification. In this case, the band seems to be about 1kHz - 100kHz or so. I've never used multisim, but I'm sure it can do Bode plots. Include one in your report and that's it. Even if this exercise is convoluted, it is also instructive: open loop amplifiers have lots of gain but are difficult to control, and their frequency response is inequal. Feedback solves both problems elegantly. Maybe your teacher is trying to make a point  .

[cvriv]

Ok. I'll include a bode plot as well. It's hard to say if he was trying to make a point with this experiment. Anyways. Thanks for your help.

[T3sl4co1l]

The frequency was implicitly assumed to be "mid band".  That is: away from the high-pass cutoff frequencies at bottom end, and also away from the low-pass cutoff frequencies at the top end.

The bottom end cutoff frequencies are defined by the RC time constants of the emitter bypass capacitors and r_e, and of the coupling capacitors and (Rout + Rin).

The top end cutoff frequencies are defined by collector and base capacitances, and the Thevenin equivalent load resistance (i.e., Rc and Rb and bias resistors acting in parallel).

Tim

[salbayeng]

Ok,
(First a big thanks to all the other posters for doing the hard yards and running sims, and spotting my goofs),
The reason this problem was set for you was not to see how good you are with a calculator, the purpose is for you to explore a real circuit, and learn from that exploration journey.  You really need to understand how these circuits work (maybe not all the minutiae just yet) as it is critical to all real world analog design.
------
Consider a bull with a ring through its nose pulling a 1 ton sled, wherever you pull the nose  ring (= base) the bull (emitter) follows (follows) just a short distance (600mV) behind , dragging the sled (emitter resistor) behind, with a  force (Ie) on the harness ,  most importantly it follows you everywhere you go,  and you just exert a tiny force (Ib) on the nose, (you could measure the HooFe parameter (hFE) as harness force/nose-ring force;  HooFe might be ~1000 for the average bull, but some have a more sensitive nose or stronger legs, and the bull is a bit slower on cold days.
You can overwork the analogy by putting the bull on a treadmill with say a waterpump (Rc) attached and tying the harness to a post (emitter bypass)  so the springiness of the harness rope (30ohms) now determines how much power you get out of the treadmill as you pull on the nose ring, you also observe that the nose ring doesn't move as far as it used to  for every newton you pull (the input impedance is much lower).  If you try to pull  the nose too far, (Vbe > 1v) , the harness rope will snap (emitter bond wire fuses) and you will get trampled (your circuit is dead).
---


One of the biggest problems for the novice is separating important details from unimportant details.
Your approach should be two step
(a) first determine the lay of the land, the "big picture"
(b) then get into the details.

So the pieces of the big picture include:
(1) is the circuit biased sensibly ?, yes this one is, the collector voltage is 1/2-2/3 of Vcc, the bias resistors are small enough to supply I_b, yet large enough not to attenuate the signal,  the collector current is in the sweet spot for this transistor (in the middle of the curves in the datasheet)
(2) What are the rough gains of each stage? , So looking at a circuit with 1k on the emitter and 10k on the collector , you can eyeball and say "around 10" ,  ignore hFE , that only shifts it by 0.5% , and the resistors are 1% anyway,  (and make a mental note to later check how much the next stage loading effects this detail)
Eyeball your circuit, and note the emitter degeneration resistor is missing (should be ~ 100ohm in series with the 10uF capacitors) (mental note: bit more care needed),  so you need to fallback to Re,  the gospel according to RAP says 30ohm (per mA) (It's closer to reality than 25mV/Ie, as other posters have noted also). You can work out the rough equivalent resistance of all those shunt terms in your head  noting that 1R shunted with 1.5R results in 2/3R , so rough gains for each of your stages is " a bit more than 100".  You don't need a calculator to do shunt resistance's R1//R2 is just R1*R2/(R1+R2) You can do each term in your head e.g. 2000//5000 = 2*5/(2+5) = 10/7 , multiply both by 1.4 = 14/10 = 1.4k
(3) What are rough impedances ?  Z out is 4k7 (mental note: check next stage Zin) Zin of transistors is roughly 100 x Re (a gain of 100 is rough enough, check datasheets later) so 3k less a bit for biasing, maybe around 2k (mental note: check source resistance (microphone is 600 , gramophone might be 47k - ouch)).
(4) What determines the bandwidth ?, so quickly eyeball where the R and C's are , use a reactance chart to determine the frequencies, write down a list of poles (and zeros). Basically 3 cases to worry about (a) coupling caps , (b) emitter bypass caps , (c) miller capacitors (mental note: as Zin > 100ohm, and gain > 10, the miller caps will dominate HF effects, need to calculate detail later, for now assume ~ 1MHz).

OK so now we have the lay of the land, total gain + 10,000 ish ,  Low freq roll off crippled by missing degeneration resistors ~ 500Hz , HF rolloff somewhere ~ 1MHz TBD,  internal impedances couple of K . 
(Mental note: gain is high and positive, reasonable risk of oscillation due input-output coupling)

NOW you can go and do the detail. hFE is between 100 and 200 , pick a number that makes calculation easier in your head (it's just as good a guess as any other)

Use the estimates from (4) to determine approximately midband.

When doing the sim, check you can see features of (4) in the AC analysis (hint use the plot [ratio of voltages] feature of the AC analysis, for each transistor plot Ve/Vb  Vc/Vb Vc/Ve; plot Vc2/Vc1 (the total gain of second stage)). The purpose is to learn what is happening, think about Cmiller where is it? what will it do to the Vc/Vb plot? where is the R that forms the RCmiller pole?  Look at the middle coupling capacitor, plot Vright/Vleft for that capacitor, this will explicitly plot the effect this capacitor has. The purpose here is to learn the art of exploring a circuits behavior. 

When messing around in the lab, use the midband frequency for Av measurement , but also swing past the HF and LF poles,  on a scope , you will see the phase shift before you notice the amplitude drop (the sine wave on the B channel will start to slip sideways)

[LvW]

cvriv, I must admit that I did not went very carefully through all the helpful contributions, but I have the feeling that - up to now - you didn`t perform a calculation (rather than a good guess) for the DC currents. Is this correct? If desired I can give you some hints for an exact calculation (as exact as possible - using, of course, an estimated value for the base-emitter biasing voltage VBE).

[cvriv]

So here's the conclusion... I went to see my professor and I handed in my report and explained everything to him. To the say the least he was very impressed with what I had did. I did everything correctly, I just didn't know that I was doing it right. LOL. He looked it over and was very impressed with the amount of time and effort I spent trying to figure it out. I just didn't know what he wanted.

He said that ultimately he wanted the gain at the mid-band frequency which is exactly what I was getting the whole time. The problem was that he didn't say that and I didn't want to assume it. By looking at my report he knew I understood how the circuit worked (within my scope of learning for that class). He said, and it's true, that I tend to want to go to far to quick with everything. I tend to go well beyond what he is teaching. He had to ground me a few times because it's gotten out of hand where I would get super frustrated etc and fall behind with what he wants me to do. I have a problem with given up. Anyways.

I did exactly what he was hoping that I would do. I told him I had to get some help online. He said all of you sound like you know what you are doing and approves that I am here talking with you for help. He curious about this "network of engineers" so I gave him the website here. LOL. Maybe he'll refer his other students here if they need help.

He also suggested hat maybe it's time to get other books to help explain things because my book has limitations.

Anyways. Thanks for you help.