Help with level shifter

[Dot]

Hello everyone,

I am building a single NPN BJT (MMBT2222A: http://www.diodes.com/_files/datasheets/ds30041.pdf) level shifter between two circuits of different operating voltages, specifically for the UART interface. The design is based on an old work in which the module's UART operated at 2.8V, but the new one's UART operates at 1.8V typically with 2.1V maximum. (See attached block diagram) 

In order to verify that the shifting will occur with new change in the module's UART voltage level, I connected the shifting circuit, as shown in the attachements, and did a physical test first.

Using an oscilloscope to display the output, I found that the signal switches from 0V to 2.44V contrary to the expected value of ~1.8V. When the circuit is tested the other way around (shifting from 1.8V to 3.3V), it works fine.

I increased the supply voltage (going from 1.8V to 2.8V) at the module side and I noticed that the output signal and the supply starts to converge, hence why the old design (2.8V) worked fine. The next step was to simulate the circuit in Spice. I downloaded a spice model of the aforementioned transistor from the manufacturer's website and simulated the circuit. At the output, it showed a transition from 0V to 2.34V, almost close to the actual result of 2.44V. I started playing with the value of R1 and I noticed that while it decreases, the output starts to converge down to 1.8V.

In this situation, I'm agnostic in respect to why the output of the circuit behaves in this way. Could it be because at a supply of 1.8V and with a 4.7K pull-up resistor (R1), the transistor will work in the active region when there's a 3.3V pulse at the emitter? I expect that it should be working in the cutoff region at this condition.

I hope you point me at which parameters I have to look at. I don't have much experience reading BJT's datasheets and I always worked according to rule of thumbs and trial and error.

[mikerj]

With the base and emitter at 3.3v, the base-collector junction is forward biased so current from the emitter supply rail is being injected into the collector load.  If you reduce V2 to less than 1.8+Vf (i.e. less than about 2.4v) it will prevent this happening.

[Dot]

I attempted your suggestion by setting V2 to 2.3V, simulated the circuit and the output was almost perfect 1.8V high. However, the design is set to deliver 3.3V to V2 and this can't be changed. At this stage, I'm free to change the resistor values only.

I understand that when the voltage at the emitter goes from 0 to 3.3v, the base-emitter junction will become reverse biased (cutoff) and no current will flow from collector to emitter, thus pulling the output to 1.8V. In this situation, how could the base-collector junction be forward biased and current from emitter being injected into the load? it goes against my understanding that no current will flow from emitter to collector, especially since the transistor is ideally an open switch in this case.

Note: let's use this circuit for a reference instead (removed R3):

[Ian.M]

https://www.eevblog.com/forum/beginners/why-a-bipolar-transistor-is-not-symmetricalreversible/

Basically if you swap C and E, a BJT will work to some extent,  maybe as well as a low gain Chinese factory floorsweeping with a breakdown voltage <10V

Deliberately made reversable BJTs do exist, see:
http://www.electroschematics.com/9660/muting-transistor-attenuator-circuits-2sc2878/

[miguelvp]

There is an app note from Phillips for I2C level shifting using a MOSFET.

The following site has an example and a link to the old appnote, there is a newer updated appnote from NXP
https://sites.google.com/site/fpgaandco/level-shifting-i2c

Old Phillips app note 97055:
https://www.adafruit.com/datasheets/an97055.pdf

Newer NXP ones:
http://www.nxp.com/documents/application_note/AN10441.pdf
http://www.nxp.com/documents/application_note/AN10418.pdf

One of those might be a rewrite of the original one, didn't open the files since I'm on my tablet right now.

What transmission speed are you aiming for on the UART? because I think this is limited to around 400Kbps but not sure.

[Ian.M]

Remove R2, bodge in a Schottky diode in place of Q1, cathode to the emitter pad.

[Dot]

It was suggested not to change anything on the level shifter circuit, not even resistor values, so that the printed circuit board will always be compatible with the old and new modules alike. Instead, I will be inserting another circuit after the level shifter on the module's own circuit board to bring down the pulled-up voltage (2.8V) down to 1.8V.

At this point, I'm considering an IC level shifter, but I would be glad to hear your suggestions given that the UART is sending and receiving at a baud rate of 921600 bit/s.

[Rick60]

Have a look at the LSF0102DCUR ( FARNELL 249-9908 )   from Texas instruments  it claims level shifting upto 100Mhz
http://www.ti.com/lit/ds/symlink/lsf0108.pdf

 

[Ian.M]

Yes an IC level shifter would be better, but you've already got the existing level shifter in the field.

It has a base resistor, limiting the unwanted pullup current.
==> Simply clamp the 1.8V module's input.

[Dot]

I actually just ran a physical test by connecting a 20K pot to R2 instead of the fixed 4.7K. I found that while R2 is increasing toward 20K, the output starts to decrease down to 1.8V. A spice simulation reveals the same result. I am assuming that a 30K-40K R2 (base resistor) would be able to decrease the output closer to 1.8V, at least not more than ~1.9(x<5)V (not looking for perfect 1.8V, just something that the module can tolerate with a bit of safety margin. Again, the module's UART is rated for 2.1V max). 

While the pot of R2 was set to 20K, I increased V1 up to 2.8V (mimicking the old module) and the output was almost perfect 2.8V high. It seems that it all leads to mikerj's explanation, but I can't understand how a higher base resistor value would bring down the output closer to 1.8V.

 

[Dot]

OK, one last question. I am switching the transistor at 500 KHz (to mimic the baud rate to be used) and I am getting an overshoot that exceeds the maximum rated voltage of the module's UART by ~1V for ~0.5us. I think that an overshoot is not a problem for recognizing a high logic (correct me if I'm wrong), but how bad is it to exceed the maximum rated voltage for a short time before settling down? possible chip damage?

[FrankBuss]

Are you sure the overshoot is in the circuit and not a problem of the measurement? Did you use the short ground connection extra for your probes, or the long cable with the clip? Another problem might be for higher frequencies that it is not a push/pull output. I would simply use a 74LVC1T45 instead of your circuit.

[Dot]

I am doing a white box test on a small part (level shifter) of a bigger system. The PCB is filled only with the components under test as in the schematic and the setup isn't that great to be honest. To provide power and signal to the SMD components, I'm connecting thin copper wires directly to the pads/pins on the PCB. As for the scope's probe, it's good quality and the ground connection is a typical 22cm alligator clip with no existing short ground tip. I might look for a prob that has a shorter lead if it would help.

Given all that, I would say that the setup might be contributing to the overshoot to an extent, but I can't guess how much.

[FrankBuss]

You should have something like this for your probe:

If not, connect at least the ground clip as close to the transistor as possible to avoid long ground loops.

[Ian.M]

With the 3.3V side at logic '1', as you starve the transistor of base current, its collector  current (E pin in reverse conduction mode) drops.  That current (+ the base current) flows through the pullup on the 1.8V side to the supply rail, lifting the emitter (C pin) above the rail. As its HFE is much lower in reverse mode than in forward mode, you can find a base resistor that limits the rise above the 1.8V rail but when the 3.3V side is at logic '0', and the transistor is in forward conduction mode, still permits it to pull the 1.8V side down to an acceptable logic '0'.

However as transistor HFE is not a closely controlled parameter, you cant predict the actual excess voltage on the 1.8V side for a logic '1' for a particular unit, so need to clamp it.   An Schottky diode from the 1.8V side output to its rail is needed.  Ideally, place this on the 1.8V module, but it could be bodged on top of the 1.8V side pullup resistor if there is nowhere else to put it (assuming you can find a Schottky in a 2 pin SMD package comparable in length to the pullup resistor size).

Assume the reverse HFE cant be greater than the max forward HFE, calculate the base current for the lowest value base resistor ever used in a production unit with the reverse emitter (C pin) clamped 1 Schottky Vf above the 1.8V rail and rate the diode accordingly.

[Dot]

Thanks Ian.M for the explanation.

Anyway, I'm now looking at a translator IC (datasheet: http://www.nxp.com/documents/data_sheet/NVT2003_04_06.pdf) and there is a parameter called 'pass switch current (I_sw(pass))'. What does this indicate?