Just a guess but wouldn't pin outs be placed according the the chip layout to take the shortest possible route minimizing the wiring inside the plastic case.
Back when silicon was expensive, this was probably a big motivation.
I suspect a lot of CD4000 pinouts were designed this way. What a cluster!
It was later realized that silicon is cheap, pins are huge, and PCBs are even huger; there is much savings to be had by doing all the hard routing work on die.
Not that this is a universal method. A lot of MCUs have shitty pinouts. Comparing an orderly ATMEGA in QFP to a messed up MSP430 in QFN, I literally waste more space on routing signals all the way around the chip, than the package size difference alone! (Given the same 2 or 4 layer design, that is. Of course, the QFN unconditionally saves space when more layers are available, especially if blind vias or HDI are used. But, those are expensive, too.)
Arguably, some of that can be "fixed in software", but it's a big pain shuffling around port bits. One option costs development time, the other costs physical space...
On a related note, you sometimes see chips in different SMT packages, and one has a rotated pinout, or something weird like that. Usually this happens when the die is rectangular, and just barely fits inside the package in question -- but only in one direction, so the pins have to be bonded out differently.
Tim