There can be subtle nasty timing problems when using 68* peripherals on Z80 busses. I can't remember the details since I last looked at them in ~1983, but hold times are probably involved.
This is the sort of thing I hope to discover when tinkering with the system, I'm only 17 at the moment (currently studying A Level's including Systems and Control, which is kind of like a mixture of electronics and mechanisms) and only really got into electronics about a year and a bit ago. The more I can learn the better! Is it something to do with the Z80 sending information when it's not requested or vica versa?
That's a good age to start with this sort of thing, and a good choice of project. You will stretch yourself, make many mistakes, and learn a lot.
When it comes to university applications, CVs and job interviews, you will be able to
demonstrate that you like this subject so much that you do "more than the minimum necessary" - that puts you ahead of 95% of people. Don't hide your mistakes, but use them as a way of
demonstrating that you are always looking out for better ways to do things in the future - learning from your experience is a valuable attribute. You'll also have something to talk to the interviewers about - and sometimes it is good to find
anything a candidate can talk about!
As to your last question, the problem isn't about info not requested, but is about the odd few ns here and there. As I say, I can't remember the detailed problem. You'll have to look at the timing details in the data sheets.
Very briefly, with digital logic typically:
- inputs expect the data to be stable before and after an edge - the setup and hold times which will be defined in the datasheet
- outputs are only stable a certain time after an edge - the maximum and minimum propagation times, which will be defined in the data sheet
Problems arise if the max propagation time plus setup time is shorter than the time between edges. Problems arise when the minimum propagation time is less than the hold time. Normally all devices from a single "family" (e,g, Z80 or 68*) are designed with a "similar internal structure", and will fit together just nicely. OTOH, different families have different "philosophies" and that can be the source of problems like this.
The best way is to draw
on paper the timing diagrams for the key signals (typically a clock, then data, r/w, cs and similar). Start at the "master" device (the processor in this case), include all the logic between the processor and end at the "slave" device (ACIA). Show the minimum propagation delay, the maximum propagation delay and realise the signals can change anywhere between the two. If you think about it, the more devices in the chain, the wider that "gap" will become. Then look at the signals when the reach the ACIA, and see whether the setup and hold times are violated; if they are then you may have more or less frequent failures.
Later on you will use simulators for much more complex circuits, but starting by doing it "the hard way" has three benefits: you won't have to fight the simulator (yet!), you'll understand what the simulator is doing (later on), and you will have learned where problems are more (and less) likely to lie.
When it comes to building something, make sure you have good solid short ground connections between
all the ICs (preferably a ground plane) and that you have a decoupling capacitor next to
each IC with the shortest possible leads. Failure to do that has lead to many sleepless nights and disappointments!