How much noise on power rail is normal?

[David Hess]

I'm no RF expert either, but I'll try my best The RF signal strength doesn't tell you anything of the quality of the signal. It may be distorted or mixed with several reflected waves of the same signal and so on. Some modulations are quite sensitive to such issues and other are able to cope with that within some limits. AFAIK GMSK is one of the latter. The demodulation needs some margin to be able to detect the frequency changes of the signal properly. If you're doing the demodulation in software (not the SDR way), I'd think that the required margin is larger than for other methods. Maybe some RF expert could chime in and give us more hints or even some numbers.

I have run across this before in FM receiver chains (which includes variations of FSK including GMSK) where RSSI was based on some rectified output from the IF signal chain but "quieting" was measured at the output of the demodulator before data slicing.  High ambient RF and and mixing products would push the RSSI up without any indication of overload from the demodulated output and sensitivity would be compromised.

I would expect a direct conversion design to suffer from this much more and the AGC to add further confusion.  The third order intercept performance of the mixers becomes more important as less RF preselection is available.  The SI datasheet implies some kind of magic at the first mixer but I suspect that amounts to lowering the gain to avoid obvious overload as there is mention of using an AGC.

[David Hess]

I have a cheap handheld radio (UV-5R+) that can send on the channels in question (A 161.975 and B 162.025 MHz), though no AIS messages. When using it as signal source the received RSSI on the same channel is -10dBm, on the other channel the receiver reports -80 dBm.

The radio specifies "spurious emissions" as < -60 dB. The Si4362 specifies 60 dB adjacent channel selectivity with 12.5 kHz channel spacing. So that seems to be within spec. No idea if that's a good or weak spec

What I think may be happening besides gross overload is that other inputs are mixing in the first mixer to produce noise directly on the frequency you are trying to receive.

What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.

Will look into this.

I do not know about newer ones but older editions of the Radio Amateur's Handbook had some details about doing this.  Many years ago I designed and built one for 2 meters which made an incredible difference under adverse conditions using the information there and some other sources which are summarized at this link:

http://www.rfcafe.com/references/electrical/helical-resonator.htm

Toko makes relatively inexpensive but suitable helical filters for printed circuit board mounting which cover 163 MHz.  Rough tuning may be done if you have a suitable signal source.  The one I built could handle 20 watts so I initially used a transmitter and SWR meter.

[chicken]

    @Christe4nM indeed! I owe you (and a few others on this thread) a beer.

Re rerouting for ground return path: In the app notes about proper grounding it usually says to avoid noisy return paths to go through sensitive areas. The other way around, sensitive return paths going through noisy areas (like arguably in my design) I didn't see mentioned.

The LDO being at the other end of the PCB makes it tricky to route a separate radio GND path without major detours for some return paths, e.g. the radio/MCU signal lines. In my next layout I could move the LDO to the left, between MCU and radio. Is that the right approach?

No worries about sunk cost or wasted components. I do this to learn something and the prototypes are functional enough that there are willing takers.

[Christe4nM]

    @Christe4nM indeed! I owe you (and a few others on this thread) a beer.

Thanks, you're welcome. I really like these PCB layout topics. Thinking along and reading other replies really helps understanding this stuff. Fellow forum member free_electron also has posted great posts about several of these topics. That is how I started to learn. Note that I’m still learning. I’m currently working my way through ‘EMC and the printed circuit board’ by Mark I Montrose. So my mind is trying to digest all this stuff anyway.

Re rerouting for ground return path: In the app notes about proper grounding it usually says to avoid noisy return paths to go through sensitive areas. The other way around, sensitive return paths going through noisy areas (like arguably in my design) I didn't see mentioned.

It all comes down to preventing the coupling of noise into the sensitive traces. Routing a sensitive trace under or right next to noisy stuff is in essence the same as putting a noisy trace through a sensitive area. The latter can be compared to the proverbial elephant in a china shop. But you don’t want to stack your china right next to a happily jumping around elephant’s paddock either

The LDO being at the other end of the PCB makes it tricky to route a separate radio GND path without major detours for some return paths, e.g. the radio/MCU signal lines. In my next layout I could move the LDO to the left, between MCU and radio. Is that the right approach?

There isn’t just one ‘right’ approach as I’m afraid.  There are some common steps to guide you though. As you’ll see a layout is almost always a tradeoff between certain best practices. Certainly on a 2 layer board you just cannot help but having to make a compromise here and there. It will help though to take a moment to think it over first.

Even then, I did a over-engineered conceptual 4 layer layout for a very simple, really simple, USB to UART board. I went through several revision before I got the board out. I learned from that, that sometimes it’s just as hard to distinguish what is actually important in your current design as it is to understand all matters that might be going on. That being able to distinguish comes from experience and practice. Something I’m still trying hard to gain anyway

OK on to the practical tips.

- If your board shape is known, spend some time with paper and pencil to determine which sub-circuits are to be placed where. Draw important signal(busses) too. See Robert Feranec’s video on PCB layout planning for an example of what I mean. (Sorry no link provided since I didn't want it embedded in my post. Just search for "pcb layout planning" on YT) This planning beforehand helps in simple circuits as well as for really complex circuits.

- Connector placement is usually predetermined, so those go as very first. Make sure that after placement of all connectors each cable plug can still fit even if all other connectors are plugged as well. This is a trap as the cable plugs are usually quite a bit broader than the actual connector on the PCB. Placing those connectors to close together could mean that you can't have everything connected at the same time...

- This pre-planning is also where you already think a bit about how/where to place the power rails.

- Since high frequency stuff is the most noisy you want to place and route those components and traces first and keep them as short as possible. I.e. crystals, clock traces, and signals needing a specific controlled characteristic impedance.

- Same goes for communication buses: usually they are busy, higher frequency digital and thus inherent more ‘noisy’. Personally I even try to route them without via’s in the trace, except for possible one very close to the pin of the ICs involved. This is more personal preference and certainly not always possible, but for very high frequency stuff via inductance might play a role. I’m still learning too, so let’s just keep this as my personal preference for now.

- Those higher frequency traces are best if routed above a ground plane / pour. That pour has to be connected to the gnd pins of the IC’s at both ends of course since it will most probably contain the return current. This is because for high frequency the return current seeks the route of lowest inductance. This is actually right beneath the trace. For low frequency this does not apply as those currents seek the path of lowest resistance back to the source. In case of a pcb that is usually the shortest path as resistance increases per length unit.

- As said: keep decoupling caps as close to the pins as possible. Larger, bulk caps can be placed further away.

- Optionally you can rotate the MCU by 45 deg. To make accessing the pins a little easier along the sides of the board. Do whatever works best for you.

- Where you place the LDO is a tough one. It doesn’t need to be that close to any IC as the local decoupling caps will keep the line ‘clean’. I personally would say that the SPI bus from the MSP430 to the RF IC gets priority in routing. What if you push the USB D+ and D- all the way ‘down’? That means they get a bit longer, but also out of the way of the other stuff. You now have an area between the MCU at the left, the USB connector at the right, the USB signal traces at the bottom and the 100mil header at the top. This could be your LDO’s new home?
Your power rail has to cross the width of the PCB one time or another anyway as the MSP430 has its VCC on the ‘top’ as I interpret the layout, and the RF IC on the ‘bottom’. As you have communication buses on both sides of the MCU I think that going under the MCU itself is basically the least worst option. I'd go on the bottom side though and make sure that there is a return path for the current.
Or try both your own idea and mine. See what works best and let us know.

- Semi-Final note. I see that you have a small stub of ground pour between the USB signal traces. That one is best removed as it can pick op noise. If you have other 'stubs', it's good practice to put a via to a ground plane (if available) at the end.

- Final note regarding the USB connector shield and ground tie: that USB to UART board I mentioned was to gain an understanding of EMI, and ESD protection. I made a topic about that in the past, but still have to reply with the final board layout. I'll have to come back to that.

edit: typos

[tautech]

I really like these PCB layout topics.

Me too.

spend some time with paper and pencil to determine which sub-circuits are to be placed where.

I have started laying out sub circuits to best final layout(pre-routing), then select all of each sub circuit and drag to an place out of the way and "park" them individually.
When ready for them, drag them back to final position, rotate if needed and  .
Mostly, only little modification is needed.
If you have sub circuits you use frequently, you can build a library of them.

[AndyC_772]

1) Decoupling cap layout.
First thing to note is that decoupling caps should always be placed between the powersource and the MCU/IC.

Make sure the traces always go through the pad of the capacitor. Think of a tollbooth at a highway. You don't want to place that using a off/on ramp, since the majority of traffic will drive right past it. You want to place those tollbooths right on the highway to make sure everyone must go through.

Lots of good stuff here, but I think it's worth elaborating a little when it comes to decoupler placement and routing, because the proper way to position them depends on exactly why they're being used in the first place.

The topology you've mentioned, where a power supply is routed to a cap, and then from the cap to the load, isn't what I'd refer to as a decoupling cap. I'd call it a filter cap, because its function is to filter out noise that's being presented to the load by the PSU. And in that case, I completely agree that your topology is correct.

A decoupling (or bypass) cap is one which exists to supply the short-term current draw from a load whose demand includes high frequency spikes - such as a digital logic device that's switching at regular intervals. In this case, the key criterion is to minimise the inductance between the device pin and the capacitor, for both power and ground. Here it doesn't matter where the cap is in relation to the (dc) power supply, it's getting the inductance down to a minimum that's key.

It's surprising how few PCBs are laid out with this in mind, because there are real benefits to be had from getting it right in terms of EMC. Here's a few tips...

- the lowest inductance path between two points is usually through a solid plane. It may, therefore, often be much better to route from the IC pin to a via, and from the decoupling cap to another via, than it is to route from the IC pin direct to the cap. It's amazing how many engineers have a mental block about this, and insist on routing from the IC to the cap "so the IC 'knows' to get its current from the cap" or some such unscientific gobbledygook. Electrons don't "know" anything, they move around according to the laws of physics.

- most SMD caps are limited in their ability to perform high frequency decoupling not by the cap itself, but by the layout. A really, really worthwhile experiment to do is to look up the typical inductance per mm of a PCB trace, then model that in Spice and see just how much less effective a (say) 10nF capacitor becomes if it has even 1mm of trace attached to each end. Seriously, it's a real eye-opener.

- With that in mind, it can be deduced that one decoupling cap that's connected into a plane with two separate vias at each end is very nearly as effective as two separate caps each of which has only one via. Save yourself some decoupling caps this way.

- Best of all, is to have two small copper planes on the component side of the board at each end of the cap, with multiple vias used to stitch these into the power and ground planes.

- The real benefit of smaller value capacitors is that they come in smaller packages, which have lower ESL. This is why they're generally regarded as being better at high frequencies. You're not achieving anything by putting a 10nF cap where a 100nF cap would physically fit. (I know this point is controversial, but if anyone can show me a convincing argument otherwise then I'm genuinely interested to hear it. Actual measurements of a real board with a suitably expensive impedance analyser could count as convincing!)

[m12lrpv]

Thanks guys for some great information. Plenty to think about that's for sure.

[Christe4nM]

<great post about bypass cap layout taking inductance in mind>

Thanks for posting this valuable information. I didn't know this, so I went and tried to find out what known experts say on this (not that you might not be, but just to make sure that others confirm this ) I found that Henry Ott (in his book Electromagnetic Compatibility Engineering) basically says the same, as well as Howard Johnson in one of his articles here.

Now I do wonder if this topology of IC pin directly to reference plane, and bypass cap "via'ed" to plane as well, is still valid or viable (no pun intended) for sub MHz decoupling. Of course the laws of nature don't change, but this topology seems to be mentioned solely in the context of high speed digital, with high speed in this case being >100 MHz. Anyone know this?

My best guess it that it still is, since fast edges are where the bypass caps come in. And those fast edges are containing these high frequency components where that (parasitic) inductance plays a big role.

[chicken]

What I would try is building a helical resonator for 162 MHz or finding an appropriate bandpass filter and inserting that between the antenna and receiver.

Toko makes relatively inexpensive but suitable helical filters for printed circuit board mounting which cover 163 MHz.  Rough tuning may be done if you have a suitable signal source.

I wasn't able to find the part from Toko. But I found this bandpass filter from Mini-Circuits:
http://www.minicircuits.com/pdfs/SXBP-162+.pdf
Is this a suitable filter, or is the <3dB passband of 155-169 MHz too wide?