Hi. I read through the topic and I'd like to chime in regarding noise. I don't know anything useful about RF so I cannot answer if mitigating noise is going to help the RF signal strength issue. Yet I do see some possible noise-related issues in your layout.
So how much noise on power rail is normal?
First of all regarding the amount of ripple and noise that is 'normal': this is purely determined by what the circuit excepts. Example given: if you have 2Vpp ripple on rectified AC before a regulator that might be perfectly 'normal'. Yet your 3.3V MCU has operating limits for the supply voltage so it needs to be within that limits.
That said, it does not mean that you can just leave all kinds of ripple and noise on the supply rail as long as it is say 3.3V +-10%. But noise in itself is not the problem... It becomes a problem when there is an electronic circuit that needs needs to operate and function correctly. Further along the line there are EMC regulations too, to make sure the circuit does indeed behave as intended even with all kinds of noise present. That, and to make sure that your circuit doesn't disturb other circuits as well.
OK, on to some practical stuff. I look at your layout and a few things got my attention. I'll try to keep it not too long as there is plenty of great material already present on the forum.
1) Decoupling cap layout.
First thing to note is that decoupling caps should always be placed between the powersource and the MCU/IC. Also the smallest cap (in value) must be placed closest to the MCU/IC. Why? Well their function is to provide the (initial) current for fast changing loads, giving the regulator time to react to the changing current demand. These fast changing loads are for example your digital communication circuit where every time it switches from 1 to 0 and vice versa the current demanded by the IC from the supply changes. To prevent these changes echoing through the supply the bypass caps are placed to provide that current. Another way to look at it is that they provide a bypass path for high frequency on the supply rail. So those frequencies cannot go beyond the capacitor and enter the supply rail. Note that it works both ways. The IC will no longer 'push' high frequency ripple on the rail, but high frequency ripply won't get to the IC either. This is only part of the picture which I will explain below.
So what you want to do is always place the smallest cap right next to the IC's supply pins, if possible directly over the VDD and GND pins. In other words: Regulator -> Largest value cap -> smaller value cap -> smallest value cap -> IC pins. Make sure the traces always go through the pad of the capacitor. Think of a tollbooth at a highway. You don't want to place that using a off/on ramp, since the majority of traffic will drive right past it. You want to place those tollbooths right on the highway to make sure everyone must go through.
* In your layout you should swap the places of C11+C12 and C10 (if I'm correct to assume that the psysical larger cap is indeed a larger value cap.)
* You should also move C21 so that is sits between the regulator and C22+C23.
* I can't see what C20 is doing, but if it's a bulk or bypass cap, consider moving/rerouting
* Same for C31
2) Why those datasheet values (sometimes) don't work - pt1
What I said above is actually oversimplification of what is going on. In reality it all about the smallest impedance as seen by the frequencies superimposed on the power rails. What you want is that if you have a ripple or noise of some frequency on your rail, that it can be 'shorted' to ground somewhere. Where? well right at the source is the best. How? By providing a path over very low impedance specifically for the frequencies of interest.
This is where the bypass caps come in. Each capacitor has a specific impedance curve over frequency that looks like a V. A capacitor's impedance is very high for low frequencies. That is exactly what we want, since the DC must 'reach' the IC. When we go up in frequency the impedance of the capacitor drops until it reaches the minimum. This is the frequency(range) where it shines as bypass capacitor. Go higher and the impedance actually increases again due to (parasitic) inductance. So in reality that 'rule-of-tumb 100nF' bypass cap, might not do anything at all for the frequency content present in your circuit.
What I tend to do is always leave room for at least one extra bypass cap. That way I can measure the actual ripple and decide to place additional caps later.
3) Why those datasheet values (sometimes) don't work - pt2
Did you know that your 100nF capacitor is not 100nF anymore when put into your circuit? Why? Well the capacity for some capacitors (at least ceramic caps) is voltage dependent. The higher the DC voltage, the lesser the actual capacitance. This results in the impedance curve shifting to lower higher frequencies. Guess what that means for your ripple and noise? Yep, it might not be bypassed anymore as the impedance of the cap for the frequency of interest might actually be in the inductive 'early' capacitive region and much higher than expected.
4) Routing power rail traces - pt1 the journey out
So you want your supply rails as clean as possible. Well in addition to decoupling of noise, you need to route them carefully and away from noise sources. Traces underneath a crystal, oscillator or clock is a big NO. But what about that trace under your MCU? Well, better not do that either. Your MCU is quite a noisy beast, even at low (aka kHz) frequencies. That is due to the harmonic content in digital electronics. It's not just the fundamental frequency, but usually getting up to the 100's of MHz in harmonics. This all depends on the rise- and fall times of the edges of your signals. Even a 1Hz squarewave can generate GHz content of noise if its rise- or fall times are fast enough (sub nanosecond).
In addition you want to keep your 'sensitive' traces away from noise sources. There are rules of thumb for that like 'keep a distance of 5 times the noisy traces' width'. Look that up with your friend Google.
* In your case I'd reroute that power trace away from under the MCU. What you could do is putting a ground pour on the top layer right under the MCU and routing traces on the other side a.k.a. the bottom layer.
5) Routing power rail traces - pt2: where does the return current go?
A good way of thinking when routing your PCB is to think in currents going somewhere. This is because currents always flow in a loop, so it helps you to keep your head in the game by realizing that those currents must go back somehow.
OK, but I've poured a ground, that should do it right? Well, that depends. Try to visualize where the return current will flow though the ground pour/plane. If is has to make a detour to get back to its source, well rather not. If that detour takes it through noisy areas: change your routing.
6) 'Helping' the bypass caps.
It can really help to suppress noise by adding a small resistor (1R or 10R) in the power rail just before the bypass caps. You've now created a low pass filter which enhances filtering. Instead of the resistor a ferrite bead can help too. Don't be fooled by their impedance rating at some frequency: look at their impedance over frequency curve. What you want is something that presents a high impedance or resistance at the frequencies you don't want. Yet at the same time a very low impedance at the desired frequency. For DC that desired frequency is 0 of course.
Phew, this has turned into way more that I intended. Hope this helps.
To the OP:
If it were me I would start with the items I marked with a *. Yes I know, redoing a board isn't that fun: you probably spend quite some time routing it the first time, you are pressed for board space and you have already spend money on the boards and components. Still it might be worth a try.
edit1: typos
edit2: correction in item 3)
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