How to control these MOSFETS and BJTs --- Active High or Active Low?

[snoop911]

Hi,

Wondering if someone can help me decipher a motor control driving circuit...

If I'm reading the circuit on the left correctly, to place Vin on PhaseA, you would drive the AH control line HIGH.  Similarly, to short Phase A to ground, the AL signal going to the N-Mosfet must also be Active HIGH.   And AH and AL must never be driven High at the same time, or else this would short VIN to GROUND, Is this correct?

The circuit on the right however, has N-BJT AND MOSFETS connected together, so not sure how to read this..   would HW and LW be active HIGH or LOW in order to connect Phase W to either V_MOTOR / GROUND?

Thanks!
Ben

[LukeW]

When HW is high then Q6 pulls the Q3 gate low, turning that P-channel FET on, and turning the half-bridge output high.

What's the Q6 emitter connected to? Ground I guess but it's not shown.

When LW is high the N-channel FET on the low side is turned on, and the output is low.

They're both "active high" inputs to control both the high-side and low-side FETs.

But LW is connected to the Q9 gate via that 100-ohm resistor, so Q12 can override that and force the gate low when HW is high, even if LW is also high.
This provides protection against the shoot-through state.

The left circuit uses two N-channel FETs instead of one N and one P. This has a number of advantages, eg. simplifying the BOM and components logistics and manufacturability. It's easier/cheaper to get better high-power N-channel FETs, so the whole bridge is built using N-channel including the high side.

The gate driver IC (IR2101) has a number of functions, including shoot-through protection taken care of for you, driving the FET gates so they turn on well, and a charge pump to provide the right bias voltages (a little bit higher than the Vm rail) ensuring that everything is biased correctly, including the biasing of the high-side FETs (which allows N-channel FETs to be used - note that the source is not at ground, so the gate voltage has to come sufficiently high relative to the source.)

[snoop911]

Thanks!   Good catch, Q6 is connected to ground via a 180 ohm pull down.   

So the left/Cypress circuit uses the IR2101 to protect and boost the gate voltage to the source-follower mosfet...   but in both circuits, the driving logic from the controller would be active high in order to engerize the upper or lower motor phase.

BTW, my goal is to use the circuit on the right, but with a Cypress PSOC developement board that is originally intended for use with circuit on the left.   Both use a 12V motor.

The backemf from the circuit on the right is scaled down to .18 of V_Motor, while the Cypress circuit scales it down to 0.1.  I'm hoping this won't matter, since for zero crossing detection, the psoc4 just compares when the backemf voltage falls below 1.19V.

Do you see any potential gotcha to look out for?
Thanks!