When HW is high then Q6 pulls the Q3 gate low, turning that P-channel FET on, and turning the half-bridge output high.
What's the Q6 emitter connected to? Ground I guess but it's not shown.
When LW is high the N-channel FET on the low side is turned on, and the output is low.
They're both "active high" inputs to control both the high-side and low-side FETs.
But LW is connected to the Q9 gate via that 100-ohm resistor, so Q12 can override that and force the gate low when HW is high, even if LW is also high.
This provides protection against the shoot-through state.
The left circuit uses two N-channel FETs instead of one N and one P. This has a number of advantages, eg. simplifying the BOM and components logistics and manufacturability. It's easier/cheaper to get better high-power N-channel FETs, so the whole bridge is built using N-channel including the high side.
The gate driver IC (IR2101) has a number of functions, including shoot-through protection taken care of for you, driving the FET gates so they turn on well, and a charge pump to provide the right bias voltages (a little bit higher than the Vm rail) ensuring that everything is biased correctly, including the biasing of the high-side FETs (which allows N-channel FETs to be used - note that the source is not at ground, so the gate voltage has to come sufficiently high relative to the source.)