How to design (start ) my own DDR controller.

[AnuI]

Hi everyone.

I want to design my own DDR controller for my project work.
I am good in verilog and will design in verilog. 
But i dont know how to start and how to approach this task.

Anyone how had worked on DDR controller from scratch could please help me with this??
I will be using Xilinx VIVADO for simulation and synthesis.

Please suggest .

[hamster_nz]

Read the memory datasheet many times over.

Start with the simplest design you can make work.

Plan how you will verify that the design is working correctly.

Test first on known-good hardware.

[Kalvin]

http://lmgtfy.com/?q=verilog+ddr

[AnuI]

Thanks hamster_nz.
Thanks for the help.

I have started reading JEDEC79E DDR specification.

If i need help.. i ll post again .

Thanks

[hamster_nz]

I found that the Micron datasheets have a quite straight and to the point description, rather than the more technical standards documents.

[AnuI]

Ok @hamster_nz.

I ll look at the Micron datasheet.

Thanks