How to fix a clipped signal

[tiofilo75]

So I am trying to amplify a sinusoidal signal to 4vpp using a multistage amplifier and I am able to get the positive 2vp but my negative side is clipped at -1.4v. I am using a FET for my 1st stage so that I may have a high input impedance, a common emitter BJT in the second stage to invert the signal from the 1st stage and finally a common collector BJT in the last stage so that I may have a low output impedance. I tried changing some resistor values to make sure that my Q point has enough room to swing in the positive and negative region by my signal is still clipped. Any info would be nice, thanks.

[qno]

To get most out of your circuit aim for Q1 collector voltage of half the power supply.
The same is true for the emitter of Q2.

You should redesign your DC set-up.

[Paul Price]

I don't see why you just don't use a rail to rail input/output type of Op-Amp to do this this job eliminating scores of resistors and capacitors and circuit sprawl?

"I am using a FET for my 1st stage so that I may have a high input impedance"

You are not going to get very hi-impedance at the input, the two biasing resistors present themselves to any input driving source  as a single paralleled resistor shunted to ground at the gate of the FET. Is this impedance high enough for you?

I tried changing some resistor values to make sure that my Q point has enough room to swing in the positive and negative region by my signal is still clipped.

I agree with the last reply...so try changing them some more to set device output pins at power supply midpoint.

My simpler circuit that solves all these problems: (attached)

Note: in attached circuit, R1 should be approx 1.1k to start with and should give close to 6V at emitter Q2.

Ok, so it is not really an op amp!