Looking for RAM.

[HardBoot]

I'm looking for dip ram chips which are as simple as sram to use but with bigger capacities, I need something in the 16-64MB range.
Basically for bufferring data for a micro because micros have tiny amounts of integrated ram, so it needs to be pretty quick, 100+MBps range.
If there's nothing dip, anything socketable like plcc would be just fine.

If all else fails... is there dip/plcc/anythingsocketable DRAM?

[T4P]

Well basically with all the inductance of a through hole package sadly i don't think you can do 100MBPS
And bad news for ya, it's all surface mount

[IanB]

I'm looking for dip ram chips which are as simple as sram to use but with bigger capacities, I need something in the 16-64MB range.
Basically for bufferring data for a micro because micros have tiny amounts of integrated ram, so it needs to be pretty quick, 100+MBps range.
If there's nothing dip, anything socketable like plcc would be just fine.

If all else fails... is there dip/plcc/anythingsocketable DRAM?

I'm a bit puzzled by how general and unspecific your question is.

When you say "micro", do you mean microprocessor or microcontroller?

Is 100 MBps 100 megabytes, or 100 megabits?

If we assume megabytes, and 8 bit bytes with an 8 bit data bus then you would need 100 million memory access cycles per second and therefore a CPU clock speed of at least that. Using 16 bit wide or 32 bit wide data buses could reduce that requirement.

Have you looked at data sheets and application notes for the particular hardware you are interested in? There is often specific and detailed information available there.

[amyk]

DIP SRAM is not going to be very high capacity, hundreds of KB at most. 256Kx8 and 512Kx8 sizes were common in motherboards 2 decades ago for cache.

If you want cheap fast memory, use DDR DRAM.

[HardBoot]

Well basically with all the inductance of a through hole package sadly i don't think you can do 100MBPS
And bad news for ya, it's all surface mount

Dip isn't too bad electrically... lots of digital and analogue chips running at a few hundred MHz, when you have long wiggly traces with vias, do you think the package it soo much worse compared to... sop16?

I'm a bit puzzled by how general and unspecific your question is.
When you say "micro", do you mean microprocessor or microcontroller?
Is 100 MBps 100 megabytes, or 100 megabits?
If we assume megabytes, and 8 bit bytes with an 8 bit data bus then you would need 100 million memory access cycles per second and therefore a CPU clock speed of at least that. Using 16 bit wide or 32 bit wide data buses could reduce that requirement.
Have you looked at data sheets and application notes for the particular hardware you are interested in? There is often specific and detailed information available there.

Dual PICs sharing 1 memory bank which has data streamed into it by a CPLD which would be the data multiplexer for the chips. 100MBps is higher than what I need, <80MBps.

DIP SRAM is not going to be very high capacity, hundreds of KB at most. 256Kx8 and 512Kx8 sizes were common in motherboards 2 decades ago for cache.
If you want cheap fast memory, use DDR DRAM.

Using DRAM is a pain, and I don't have a ton of spare logic, it's annoying enough with FPGA... years ago I remember seeing 8 and 16MB ram chips in plcc, all discontinued.

Aren't there dram chips with built in logic to make them act like sram? I swear I've come across something like that.

[SeanB]

If the data rate is high enough, and you can guarantee that you will hit all the addresses in a row or column in less than the max refresh interval then you do not need a dedicated refresh controller. The act of reading a row refreshes all the other rows in the chip for that read/write cycle, and if you do more than 256 incremental reads no need for refresh.

[codeboy2k]

[if you can] hit all the addresses in a row or column in less than the max refresh interval then you do not need a dedicated refresh controller. The act of reading a row refreshes all the other rows in the chip for that read/write cycle, and if you do more than 256 incremental reads no need for refresh.

In the old days I just wrote an interrupt routine that sequentially scanned memory at the refresh rate. That's all that was needed.
Not the most efficient, but it worked and was simple.  The hardware we built at the time was very discrete, did not have any
memory controller on the MCU, or on the board at all, and we used rows and rows of small DRAMS on 18-20 pin DIPS I think
it was.

This was around 1986-87.

By the way, if you need this for a one off project, you can get some 30-pin 16MB  SIMM modules on eBay, like the picture. just find something fast enough and make the data bus wide enough for your speeds.

[Monkeh]

SIMM modules

Die. That is all.

[IanB]

Real computers use memory measured in MB (or was it KB?). It's only these new-fangled toy computers that need GB of memory installed before they will even boot up to a blank screen.

[SeanB]

I worked on one that had memory measured in bytes, and it used core planes as well. There was an upgrade that used a 6116 and a battery for backup.

[andersm]

Aren't there dram chips with built in logic to make them act like sram? I swear I've come across something like that.

Pseudo-SRAM is available from at least ISSI, Winbond and Fujitsu. I say available but... Any type of memory with any kind of density will also be available in BGA or TSSOP only, with x16 or x32 bus width.

[codeboy2k]

SIMM modules

Die. That is all.

I missed the joke 

Are you saying SIMM modules have a tendency to die?  Or are you wishing me to expire here  lol

[Monkeh]

SIMM modules

Die. That is all.

I missed the joke 

Are you saying SIMM modules have a tendency to die?  Or are you wishing me to expire here  lol

'Single In-line Memory Modules modules' is what you've just said. Twice.

[hlavac]

Sounds complex...

To serve as a buffer for 80 megabytes per second you will need 80M writes and 80M reads per second,
you would have to use like 10 55ns SRAM chips in parallel and read/write the data in 10byte chunks at 16Mops...

80 data lines, you could maybe share the address lines with some line buffers

[codeboy2k]

['Single In-line Memory Modules modules' is what you've just said. Twice.

aha.. I see it got your shorts in a knot. Sorry about that.

That must hurt as much as DIP package, or BJT transistor 

[Monkeh]

['Single In-line Memory Modules modules' is what you've just said. Twice.

aha.. I see it got your shorts in a knot. Sorry about that.

That must hurt as much as DIP package, or BJT transistor 

Quite. Illiteracy is a sin.