How to simulate noise on DC power bus caused by dynamic load currents?

[Metatronic_Mods]

EDIT: Sorry, I should clarify, I understand how to model the power bus and interconnects and traces. I understand how to design a filter for the desired performance given the noise spectrum present.

My confusion is with how to model a simplified equivalent circuit for the load portion of the system. In other words, I have a load which is not constant current, but has analog, CMOS and or other digital devices. Which ideally would be modeled as some combination of a (passive) load resistor and active source. And I'm wondering if I'm correct in thinking that a load resistor in parallel with an AC current source(s) at the noise frequency(ies) could suffice as a model for the load.



I'm trying to design some add in power supply bypassing for some circuit modules with insufficient on-board bypassing.

The problem is, multiple circuit elements are powered from the same DC12V bus, and because this bus has a (small but still noticeable) resistance, when the different circuit elements switch on and off, the change in current is seen as a small fluctuation in voltage on the DC power bus. This small fluctuation is enough to affect the operation of sensitive devices elsewhere on the bus.

Anyways, I'm wondering how to adequately simulate this noise, to simplify testing and adapting my solution for a wide variety of cases.


For an example, one circuit element has a DC current draw of 200mA at 12VDC. However, the actual draw is AC 10mA peak-to-peak riding on a 200mA DC offset.
So my thinking is that the DC portion is easily simulated by a 60? load (12VDC/200mA) and the AC portion can be simulated by adding a 10mA AC current source in parallel with the load resistor.  Does this sound correct?

I'm sorry but I've been unable to find much info on here or elsewhere on the web. I think my intuition is correct, but it would be nice to hear from someone with more experience whether there is a better way.

[JS]

I don't know what simulation you are running, maybe the schematic would help.

The first thing you can do is just to add a resistor to your circuit in series with the PS, as it would be the trace resistance. If you have a complex device with several things pinching from one power trace add a resistor between each device. The resistance should be the trace resistance between each split for each device, measured on the PCB or wiring.

If you are working on highish freq you should also add the inductance of the traces into account.

All this (non-zero) impedance on the PS rails is the reason to have decoupling caps as close as possible to each device. In some cases you could add a resistor in series with the rail (before the decoupling cap) feeding some section of the circuit or even a local LDO to isolate as much as possible from the rail noises. Decoupling sensitive circuits is an art, we could expand on this to fill a library, for instance, you pick the cap value so the impedance at the working frequency is the lowest. It won't be the biggest cap, as caps gets bigger also it's parasitics inductances, so you might find a smaller cap would have a lower impedance than a bigger one above a certain freq. If the working frequency is wide you might want start adding more than one cap of different values in parallel.

JS

[Metatronic_Mods]

I don't know what simulation you are running, maybe the schematic would help.

The first thing you can do is just to add a resistor to your circuit in series with the PS, as it would be the trace resistance. If you have a complex device with several things pinching from one power trace add a resistor between each device. The resistance should be the trace resistance between each split for each device, measured on the PCB or wiring.

If you are working on highish freq you should also add the inductance of the traces into account.

All this (non-zero) impedance on the PS rails is the reason to have decoupling caps as close as possible to each device. In some cases you could add a resistor in series with the rail (before the decoupling cap) feeding some section of the circuit or even a local LDO to isolate as much as possible from the rail noises. Decoupling sensitive circuits is an art, we could expand on this to fill a library, for instance, you pick the cap value so the impedance at the working frequency is the lowest. It won't be the biggest cap, as caps gets bigger also it's parasitics inductances, so you might find a smaller cap would have a lower impedance than a bigger one above a certain freq. If the working frequency is wide you might want start adding more than one cap of different values in parallel.

JS

Thanks for the reply. Right, so my idea is to come up with a range of T section filters to put in series between the rails and sub circuits. Ideally having a few different "flavors" to cover the prominent noise frequencies and harmonics I'm seeing on the rails.

I get how to simulate the rails themselves. My question is about how to simulate a dynamic load (maybe this isn't the best word, or there's a better word for it). For example:
One of the noise signals I'm seeing is evidently caused by a series of PWM driven LEDs which are switched on/off synchronously rather than staggered (bad design I think) so the current spikes for each add together and I'm seeing ~35mA spikes at the PWM frequency even after the circuit's built in decoupling.
This circuit draws an average DC current of 200mA at 12V (with the 35mA spikes superimposed on top of this).

The DC portion of the load is easy enough to model. That's just the load resistance (12V/0.2A = 60?)  But it's the AC portion, the 35mA PWM that I'm not sure about how to model.  My intuition says that I could just think of this as a 35mA pulsed current source in parallel with the 60? load resistor, and proceed with the analysis.  But I'm looking for a second opinion, since we never really talked about this scenario in school, and this doesn't seem to be a well covered topic in general as most texts treat power rails as ideal 0? wires which as far as the noise issue is concerned don't care what the load is doing or not doing.

[T3sl4co1l]

The keys is that a trace has inductance and resistance.  And at more than a few kHz, the inductance dominates!

The inductance is given by the trace's characteristic impedance and length.

Then you can construct the PDN (power decoupling network) from the components used (model capacitors as C + ESR + ESL, using typical values for their sizes and ratings -- note that MLCCs have a body length, so are basically more trace length themselves: use this for estimating ESL), and yes, loads can be modeled as current sinks and resistance.

Whether a load is resistive, depends.  Analog circuits tend to have a constant current characteristic (op-amps and such).  Digital logic (CMOS) tends to be resistive.  Switching supplies are negative resistance, but don't forget to account for their bypass capacitance as well (so, only negative up to a limiting frequency, until the capacitance dominates).

In any case, model the load as whatever combination of (+/-)R and CCS is necessary to get the correct DC and AC results.  Or ignoring DC (since it's practically trivial), concentrate only on the dynamic impedance -- resistance and reactance.

You will find that a linear PDN can be modeled as a lumped equivalent transmission line, or lowpass filter, and so all the usual matters apply: very high, or very low, impedances cause reflections; nominal resistances cause termination (damping).  More inductance and capacitance results in more attenuation at high frequencies, but itself must be dampened.

You'll typically design around the properties of components you have: say, using just enough inductance to get the required attenuation, while using enough electrolytic capacitors to keep |Z| low, and damped with the ESR.

Tantalum capacitors are preferred because their ESR is stable over time and temperature (just don't expose them to surge currents).  Alternately, you can avoid conflict minerals and surge limits by using ceramic caps + external ESR resistor.

Tim

[rhb]

First of all, I have *no* experience with this sort of a problem.  But I have a lot of experience with DSP and such. 

By superposition, you have a DC component and an AC component to the load. At present you have some filtering of the AC noise on the rails, but not enough.  PWM is a range of pulse trains.  So what you need to do is evaluate the spectrum of the "typical" pulse via Fourier transform and design a low pass filter with Fc lower than the harmonics.  A conservative approach would be to calculate the spectrum of the longest pulse which is less than 100% and design the filter around that.

Take as long a DSO sample as you can, take it to a PC and use Octave or MATLAB to calculate  the amplitude spectrum.  That will tell you what you need for filtering at that point in the circuit.  Start at the PS end.  When it looks clean there move farther out on the rails.

As a reminder of what you already know, a square wave consists of odd order harmonics up to the rise time of the square wave.  This is the same problem except it's not a square wave, so you also have even order harmonics.  Very likely if you design a filter with an Fc around the 3-4th harmonic of the PWM period you'll be fine.

[Jay_Diddy_B]

Hi,

This model will show you how to do the testing with a 60 resistor for the 200mA static load and a function generator for the dynamic load:



The FG output is injected into the 12V rail through a blocking capacitor. The 1.75V voltage results in 35mA p-p flowing in the 50 resistor.

This is the result:



I have attached the LTspice model.

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Hi,
There is a whole section of engineering associated with this problem. The power distribution network, PDN, needs to be low impedance across a broad range of frequencies. Think of it as signal integrity for power.

A capacitor doesn't always behave as a capacitor, above it self-resonance frequency it behaves like an inductor.

Here is the impedance plots for a couple of ceramic capacitors:



Quite often the solution is to let the high power loads corrupt the power supply and filter the supply needed by the noise sensitive loads.

Regards,
Jay_Diddy_B

[max_torque]

Surely the "sensitive" units should be designed in such a fashion as to remove that sensitivity to their supply?

If a unit needs a "precision" supply, then that supply must be provided for that unit?

Are we talking about different 'sections' of circuitry on one pcb, or entirely different pcbs with a common supply bus?

[Metatronic_Mods]

Surely the "sensitive" units should be designed in such a fashion as to remove that sensitivity to their supply?

If a unit needs a "precision" supply, then that supply must be provided for that unit?

Are we talking about different 'sections' of circuitry on one pcb, or entirely different pcbs with a common supply bus?

Entirely different circuits. Different different manufacturers, different engineers (many of them rubbish) and no real guidelines or best practices apart from some basic footprint and interconnect specifications adapted from a more fleshed out standard some 30+ years ago. In short, a f****** mess. But it's what we have to work with, and despite it's quirks it has it's niche uses, so it's worth taking the time to bandage up.

[Metatronic_Mods]

In any case, model the load as whatever combination of (+/-)R and CCS is necessary to get the correct DC and AC results.  Or ignoring DC (since it's practically trivial), concentrate only on the dynamic impedance -- resistance and reactance.

Sorry, CCS? Constant current source? If so, I'm confused as to how that and +/-R suffice to model my pulsed load current? Or did you mean something else?

[Metatronic_Mods]

Sorry, I should clarify, I understand how to model the power bus and interconnects and traces. I understand how to design a filter for the desired performance given the noise spectrum present.

My confusion is with how to model a simplified equivalent circuit for the load portion of the system. In other words, I have a load which is not constant current, but has analog, CMOS and or other digital devices. Which ideally would be modeled as some combination of a (passive) load resistor and active source. And I'm wondering if I'm correct in thinking that a load resistor in parallel with an AC current source(s) at the noise frequency(ies) could suffice as a model for the load.

[T3sl4co1l]

Yes, the simplest linearized model is a current source and resistance, to set the DC and AC properties respectively.

Tim