How transistors work

[Legion]

I've been trying to figure out how transistors work, but unfortunately, all the resources I've found are really just a collection of facts, but not an explanation.  Knowing that a base current can modulate the emitter to collector current is great, but it doesn't really explain why it's able to do that.

So, any good resources online that explain what's going on inside a transistor at the electron level?  Also, does a transistor actually amplify current, or does it just allow us to control a larger current using a smaller one?

[Kremmen]

You could try starting from this: http://hyperphysics.phy-astr.gsu.edu/hbase/solids/pnjun.html#c1
The browsing links are not too organized but you will find the topic tree containing the transistor as well.
The explanations are necessarily condensed as the full dissemination takes several volumes. But maybe you get the idea at least.

Wouldn't it be nice if a transistor actually amplified the current? Instant free energy... No, it just modulates a larger current with a smaller one.

[vxp036000]

I think the reason you haven't found much online is that a strong background in quantum mechanics (read: math!) is needed to describe what's happening inside a transistor.  There are two basic transistors: FETs and BJTs, FETs will need to wait for another time. 

We'll start with the BJT, the NPN transistor.  In series, there is an N doped semiconductor, P doped semiconductor, and another N doped semiconductor.  The first N doped material goes to Vcc, the P doped material goes to the base contact, and the second N doped material is connected to ground.  When I increase the base voltage, the depletion region around the PN junction from base to ground decreases, forward biasing the junction and increasing current flow.  The reverse biased NP junction from Vcc to base makes for an excellent electron sink.  This is because reverse biasing the junction increases the width of the depletion region, so any minority carrier electons in the P material experience strong acceleration toward Vcc.  So we see that increasing the base voltage increases the current flow; so we have a voltage controlled current source.

If I lost you already, I suggest first studying physics behind the basic PN diode.  BJTs are simply an extension of the concept.

I've been trying to figure out how transistors work, but unfortunately, all the resources I've found are really just a collection of facts, but not an explanation.  Knowing that a base current can modulate the emitter to collector current is great, but it doesn't really explain why it's able to do that.

So, any good resources online that explain what's going on inside a transistor at the electron level?  Also, does a transistor actually amplify current, or does it just allow us to control a larger current using a smaller one?

[TerminalJack505]

I should warn you now if you are just getting into electronics.  If you think you will be able to get a clear picture about what's going on at a physical level you are likely to be disappointed.

Much of the work in electronics was done before the electron was discovered and before QED was developed.  The work done through the centuries has a mix of theories and physical models.  The earlier theories don't even attempt to actually describe what happens at a physical level.  This can be frustrating if you are  "visually oriented" or just have to know what is truly happening at a physical level.

Just as one example, you will find that the physical forces involved in electronics can be described in various references by any of the following:

• Newton's mysterious "force at a distance" (mechanical analog, E.M.F., for example.)
• Classical field theory (properties of empty space, waves, etc., flux density, for example.)
• Field particle theory (QED, our current understanding.)

So, when you learn about transformers you are likely to learn about 'flux.'  There is no such physical thing as flux.  It just happened to be a good model for what scientists where trying to describe.  (They didn't know about electrons and their properties, let alone the force carrier, the virtual photon, at the time.)

[vxp036000]

I think an understanding at the physical level isn't much of a stretch with quantum mechanical models.  Anything less is nothing but an analogy and it's not hard to find common scenarios in which the analogy is completely invalid. 

I should warn you now if you are just getting into electronics.  If you think you will be able to get a clear picture about what's going on at a physical level you are likely to be disappointed.

Much of the work in electronics was done before the electron was discovered and before QED was developed.  The work done through the centuries has a mix of theories and physical models.  The earlier theories don't even attempt to actually describe what happens at a physical level.  This can be frustrating if you are  "visually oriented" or just have to know what is truly happening at a physical level.

Just as one example, you will find that the physical forces involved in electronics can be described in various references by any of the following:

• Newton's mysterious "force at a distance" (mechanical analog, E.M.F., for example.)
• Classical field theory (properties of empty space, waves, etc., flux density, for example.)
• Field particle theory (QED, our current understanding.)

So, when you learn about transformers you are likely to learn about 'flux.'  There is no such physical thing as flux.  It just happened to be a good model for what scientists where trying to describe.  (They didn't know about electrons and their properties, let alone the force carrier, the virtual photon, at the time.)

[free_electron]

sigh.. so all we have so far is the belitteling of people that have no math or physics understanding (the usual 'talking down'on people, and 'look at us we have a degree')
But none have given an explanation on how it works...

-edit- while i was typing this up even more 'fuzz' was added...

here we go : (without the math, QED bullshit overload )

There are two types of material :

N material is a smiconductor that has an excess of free electons
P material is a semiconductor that has a shortage of electrons ( sometimes explained as 'an excess of holes'. in reality there are no 'holes' , ony lack of electrons )

N and P material are constructed by 'seeding' ( the technical process is called implantation ) a donor material into the silicon ( or germanium or other semiconductor ). Silicon has 4 electrons on its outer shell but would really want to have 8.. so it readily forms bonds with other silicon atoms. We can create a 'free electron' by injecting a donor material that has 5 electrons on its outer shell ( like Boron. the silicon will combine with the Boron and 'share electrons'. this fifth electron is now 'free'. It is still bound by atomic forces to the phosphorous but it is also highly mobile : it can be 'knocked off easily' that is why we call it free.
We can also create bonds with an element that has only 3 electrons on its outer shell , like phosphorous. Here the semiconductor will bond and have a link with 7 electrons ( 4 of its own and 3 donors from the implanted material. So it is one short from an ideal state, but it is happier than ith only 4.

The material that is one electron short is P material ( there is a missing electron or a 'hole' there to fit one in )
The material that has an excess of electrons is N material.

Right , now that we know this we can take a look at the transistor structure.
The classic bipolar transistor is a 3 layer structure of N and P material. The denotation NPN and PNP tell you how the layers are ordered.
Lets take a look at an NPN stack.

Before we delve in in :
the properties of a conductor material is that electrons can flow freely. if all electrons are trapped you have an isolator.

So we stack a bit of n material on top of P material on top of another bit of N material. And then magic happens.
At the intersection of these mateirals the free electrons fomr the N material combine with the free 'holes' of the P material and you get actually a thin region where all free electrons have fallen in a hole. ( this is called the depletion layer ) and no further electrons can cross this barrier.

In schematic form

Code: [Select]


 NNNNDPPDNNNN
 NNNNDPPDNNNN
 NNNNDPPDNNNN


N = n material full of free electrons
D = depletion zone : n material free electrons have fallen in p material holes
P = p material 'short of electrons

So what happened here is that , free electrons form N regions have fallen in 'holes' in the P region . This has trapped them and created two depletion layers. Since the electrons are trapped you have effectively created an isolator there. The reason this forms only a thin layer is simple : as electrons combine with holes the 'pressure' decreases. Let me see how i can explain this one:

We know that like charges repel each other and dislike charges attract each other. So , in an area where you have an excess of electrons , they are all trying to push each other away. if you give them a path to escape they will go that direction. So here is this one side that touches the P material full of nice holes they can fall into : and away they go. They happely move that way , fall in a hole and get trapped. The electrons behind them can still skip over because the ones behind those are still pushing. But eventually the depletion zone is wide enough , and enough electrons have been removed from the n region that the reminaing electrons have not enough 'push' to keep this process going and it stops. It stops , provided we do not apply an external source of pressure.

And this is what we will do : I am going to apply an 'electron source' to the right hand terminal to give a bit more 'pressure'  . An electron source is the negative terminal of a power supply as electrons carry negative charge.
To close the loop i will apply the positive terminal of the same supply to the P material.

Code: [Select]

    NNNNDPPDNNNN               
  ==NNNNDPPDNNNN================
    NNNNDPPDNNNN                ||
       ||                       ||
       ||                       ||
       ||                       ||
        =======(+)source(-)======

so , by feeding more electrons into the right hand terminal i create more 'pressure' and  current will begin flowing ( the arrow above shows the way they flow). I am pulling the electrons out the P material region.

For clarity sake , lets slap a name on these terminals shall we ? Since the element i connected my 'electron source' to is 'emitting' them, i shall call this terminal the emitter. pretty logical.
The terminal i am pulling the electrons from i shall call... the base. No, not the collector.... got you there ! I will explain later why this is the 'base'.

So , by sending electrons in the emitter , and pulling them out of the base i create an electron flow. This is the base-emitter current ( in electron flow the emitter-base current, but a it was not known electrons were negative in the olden days we assumed current flows positive to negative... )

Right. Now i will attach another power source. A source that will feed even more electons in to the emitter but , this time, will attempt to pull them out of the third terminal. The 'collector' terminal , as this is where we will tempt to collect them.

Code: [Select]

  ================(+)source(-)=====
||                                ||
||  NNNNDPPDNNNN                  ||
  ==NNNNDPPDNNNN==================O
    NNNNDPPDNNNN                  ||
         ||                       ||
         ||                       ||
         ||                       ||
          =======(+)source(-)======

If i am not pulling anything out of the base i have those two darned depletion layers in the way that prevent current from flowing. if i start pulling some electrons out of the base the depletion area is being broken down (remember the depletion area is the area where no movement is possible because there is 'pressure' balance... ) and the electrons start flowing.
if i start pulling harder and harder i can move the depletion areas so much that they almost touch each other. In the mean time , my other 'power source ( the one between collector and emittor) has been wicking away electrons from the collector region ( in rest there is a surplus of electrons there. Because we 'doped' this material duering construction remember ? )

so we come to a point that electrons are being wicked from emitter into base , and they get so close to an area where there is even a bigger 'void' of electrons ( the collector is more positive than the base. More positive means less electrons avaialble , or more holes ) so electrons that were destined to go into the base actually start flowing into the collector region where they are whisked away by the power suource there. And there you have the transistor function.

The harder you pull on that base , the more electrons you pull out of the emittor. if they come close enough to the collector area they are attracted there becasue there is an even bigger 'void' of electrons there. so , by 'steering' the flow in the base you steer the flow in the collector. Amplification !

So the base current actually moves these 'zones' until they touch and then celectrons start flowing from emitter to collector. if i stop pulling there the depletion areas move inside the structure and the flow stops.

Now, there is more than meets the eye. This trickery only works under certain contitions.
That right hand terminal ( the emitter ) is actually heavily seeded with electrons.
The base is only mildly made void of electrons the collector is also only mildly seeded.

So there is more 'pressure' in the emitter than in the collector.
This base layer is also very very thin compared to the other two.

This helps the electron run into the collector as there is only so much that can flow into the base ( there are not enough holes there for all of them to fit as it is only mildly seeded with holes )
And since the collector area is only mildly seeded this area is very fast depleted by the higher positive voltage applied there. So the electron coming out of the emitter can go 2 ways : into the base or into the collector. ( remember the collector is beeing sucked 'dry' by the applied power supply . a suply that is at a higher level than the level at the base) and they take the path of least 'resistance' : the path where there are the most missing. in essence that collector 'N' region actually becomes a 'p' region while the transistor has current flowing through it.

This is your very very basic operating of a bipolar transistor. To make a PNP redo this explanation but swap 'electrons' with 'holes' and swap 'positive' with negative.

Now , on the subject of this 'base' terminal. Here's where that comes from.
The first transistor was not made out of N and P material. You can actually make a depletion area between a doped semiconductor and a metal. you don't need tow doped semiconductors. Actually the word semiconductor is used to denote an element where you can change the conductivity of. it can be isolating , or it can be conducting , dpeending on what you do with it. a metal is always conducting. an isolator alwasy iolating ( unless you 'force' charge across with extremely high voltages (voltage = pressure ))

But metal can be an electron donor.. tis is actually the principle behind a shottky diode. a classic diode is an N and P region where as a schottky diode uses only an N region and a strip of metal.
the first transisotr was a strip of P material that was laid on top of a copper plate. this strip of p material formed thus the 'base' of the transistor construction. And there you have it : the 'base'
the emittor and collector were made by putting a strip of gold foil on a triangular piece of glass. this piece of glass was pressed down with a screw onto the base. the pressure of the sharp edge did two things : it cut the goild foil in hlf and pressed the extremities into the germanium 'base'  (they used gemranium at the time )
the strip of gold 'feeding' electrons was the 'emitter' , the strip collecting them the 'collector'

Code: [Select]


collector--     ---- emitter
           \   /
 base    ___\ /____
               
and this is also where the transistor symbol comes from... the line is the base and you have two electrodes under a 45 degree angle ( they used a 90 degree corner of glass , put that under 45 degrees and pressed down , snipping the gold foil in half and creating the two depletion regions of gold-germanium )
I scavenged two links from the internet that show this first transistor ( replica's )

This one below is high resolution. You see at the bottom a slab of copper , on top of that the slab of germanium and then the triangular piece of glass with the gold foil on edge ( they metallized the glass so they could solder it to that 'wavy bit' whch is actually a spring pressing the glass down on the germanium slab.
http://www.porticus.org/bell/images/transistor1.jpg

We use the arrow to indicate where the emitter sits.
Now , that first transisotr worked both ways. there wa sno difference between emitter and collector apart form where they applied the correct polarity. This came only later as tey sought to improve performance. that is where they started making the assymetrically shaped construction of having a heavily doped emittor and a weakly doped collector. but that is another story ...

So there you have it : the transistor in simple terms , without requiring a degree in maths and physics. You can of course now slap on the maths and start calculating the field strengths and electron levels and all the other stuff , and figure out what is the optimum layer thickness, implantation strength but that is just a numerical representation of what is happening.
Electrons are very simple elements that never went to school and don't know anything about maths or physics. They repel each other and if they see an area where there is 'room' they simply go that way.

No doubt there are going to be people that will start complaining about quantum effects and other things. The above explanation is according to the 'electron model'. A Model that is understandable without 'fuzz'. If you think you can do better , please feel free to write a posting here with a more accurate model.
 
           

[IanB]

Bravo, free_electron, an explanation without mathematics!

This is important, because if you think you need to resort to mathematical models to explain how something works, you don't really understand it. Mathematical models are used to calculate the details of what something does, not to explain how it does it.

By the way in case it wasn't obvious, N type material is so called because it has negative charge carriers, and P type material because it has positive charge carriers. Then you can view the depletion layer as being a zone where the negative and positive charge carriers cancel each other out and leave no charge carriers. No charge carriers in a material makes it an insulator.

[vxp036000]

The difficulty a lot of people run into when they try to avoid the math is that they come up with an explanation that violates some fundamental law of physics, without realizing it.  free_electron's explanation is a great analogy for many situations, but it's important to realize the limitations of the analogy.  Furthermore, I would say that someone doesn't truly understand something unless they can explain it in terms of fundamental laws of physics, which, by the way, are defined as mathematical models.

For example, the analogy doesn't explain band gap references, why transistors perform so poorly when collector and emitter are interchanged, thermal runaway, the active region of a BJT (needed for any amplifier to work), etc.  The mathematical model explains all of these exceptions without needing to resort to another analogy and having to explain why the analogy is no longer valid.

Bravo, free_electron, an explanation without mathematics!

This is important, because if you think you need to resort to mathematical models to explain how something works, you don't really understand it. Mathematical models are used to calculate the details of what something does, not to explain how it does it.

By the way in case it wasn't obvious, N type material is so called because it has negative charge carriers, and P type material because it has positive charge carriers. Then you can view the depletion layer as being a zone where the negative and positive charge carriers cancel each other out and leave no charge carriers. No charge carriers in a material makes it an insulator.

[Kremmen]

free_electron: I actually read through your post. Not bad. It really should be enough for anyone who wants a basic grasp of a BJT. Somehow i felt the OP had reached this level but still wanted to know how it "really" works.
I didn't see so much belittling in the previous posts - certainly i didn't try to be that way. The fact just is that if you want to know what is "really" going on, then enter the next level of description. Whether that is useful for a practicing designer i am not at all sure, but that was the way the question was put.
While i mostly agree with IanB regarding narrative explanation of things, there is a limit after which it does not help further. Narration is qualitative, not quantitative. A transistor circuit designer will need things like hfe, VCEmax etc etc on top of the explanation of how it all works. He won't find quantum mechanical explanations, much less formuals very useful because they describe the same thing on a different level that is not relevant for practical design. Yet the level is there. The problem with everything quantum is that it wasn't designed to be readily understandable. Some of it is literally beyond reason as i am sure you know (just consider the photon diffraction experiment http://en.wikipedia.org/wiki/Double-slit_experiment). Still, the bottommost explanation is the only one that covers every aspect, simplified models will miss parts of the reality.

[IanB]

The difficulty a lot of people run into when they try to avoid the math is that they come up with an explanation that violates some fundamental law of physics, without realizing it.  free_electron's explanation is a great analogy for many situations, but it's important to realize the limitations of the analogy.  Furthermore, I would say that someone doesn't truly understand something unless they can explain it in terms of fundamental laws of physics, which, by the way, are defined as mathematical models.

For example, the analogy doesn't explain band gap references, why transistors perform so poorly when collector and emitter are interchanged, thermal runaway, the active region of a BJT (needed for any amplifier to work), etc.  The mathematical model explains all of these exceptions without needing to resort to another analogy and having to explain why the analogy is no longer valid.

That's not really a sufficient view of the world. As Kremmen says, there are layers of explanation and you need to pick the layer that suits your purpose. There is no need to pick a more detailed model to satisfy a simpler need. Engineering is all about picking the right level of abstraction to suit the task at hand. Also, fundamental laws of physics are only "fundamental" until someone finds more fundamental laws underneath.

Someone above suggested that magnetic flux is not "physically real", but that virtual photons somehow are. Isn't there a certain amount of absurdity in that? Philosophers can spend forever debating what is "real" and what is not, but when it comes down to it all mathematical descriptions of physical behavior are abstractions. Mathematical models create an analogy of physical systems using a formal technical language, where we hope that what the model does in the abstract will be reflected in real life. We have got quite far down into the fine detail these days, but that does not mean we are finished.

free_electron: I actually read through your post. Not bad. It really should be enough for anyone who wants a basic grasp of a BJT. Somehow i felt the OP had reached this level but still wanted to know how it "really" works.
I didn't see so much belittling in the previous posts - certainly i didn't try to be that way. The fact just is that if you want to know what is "really" going on, then enter the next level of description. Whether that is useful for a practicing designer i am not at all sure, but that was the way the question was put.
While i mostly agree with IanB regarding narrative explanation of things, there is a limit after which it does not help further. Narration is qualitative, not quantitative. A transistor circuit designer will need things like hfe, VCEmax etc etc on top of the explanation of how it all works. He won't find quantum mechanical explanations, much less formuals very useful because they describe the same thing on a different level that is not relevant for practical design. Yet the level is there. The problem with everything quantum is that it wasn't designed to be readily understandable. Some of it is literally beyond reason as i am sure you know (just consider the photon diffraction experiment http://en.wikipedia.org/wiki/Double-slit_experiment). Still, the bottommost explanation is the only one that covers every aspect, simplified models will miss parts of the reality.

This is the key thing, about finding levels of description that meet your needs.

I agree about qualitative vs quantitative. That's what I meant when I said mathematical models serve the purpose of "what will happen" rather than "how it will happen". Understanding how things happen is a much deeper and more complex problem that requires insight, scientific intuition, abstraction, analysis and many other skills beyond computation with formulas.

[T4P]

http://amasci.com/amateur/transis.html

Don't let anyone tell you they are current controlled

[free_electron]

band gap references,

the explanation is on transistors , not bandgaps. if you want to study bandgaps you need to delve into chemistry(how the atom is built) and physics (how electrons interact with the nucleus of an atom)

why transistors perform so poorly when collector and emitter are interchanged

that is actually explained... has to do with the different doping strentgh between collector and emittor. in a point contact or cat whisker transistor there is no 'emitter and collector.. you find out which is which by TRYING it out... you can't control how hard you press and where you create the better doping. only when planar transistors were invented and they performed the doping during deposition in the oven ( only later came ion implantation machines. i did maintenance on those beasties for a while. i actually started in the waferfab maintaining and repaireing the ion implanters and plasma etchers... that was fun. very clever technology like the mass analyzer to select what you implant , the dosimetry technique used. rotating magnetic fields to create uniform plasma dispersion )

thermal runaway,

has nothing to do with the fundamental working.
you are adding 'fuzz' to the basic operation. if you want to add fuzz : how about other impurities ? they create noise ? how about tunneling effects ? how about 'hot carrier injection ? . it does no good to

The mathematical model explains all of these exceptions without needing to resort to another analogy and having to explain why the analogy is no longer valid.

try to teach someone math by starting with integrating quadratic equation and see where you end up... nowhere.
Start with numbers and + - * / then work your way up. This is what i did here. Starting with the absolute basics.
Now you can explore if you want why electrons repel each other , how the recombination works on a physical level. Then you can add on what other dopants there are , when to use them andwhy. and then you can start looking at geometry of the electrodes. and you can pull in field theory and other stuff as well. But it does no good to start with a 500 page manual of equations.

Bravo, free_electron, an explanation without mathematics!

This is important, because if you think you need to resort to mathematical models to explain how something works, you don't really understand it. Mathematical models are used to calculate the details of what something does, not to explain how it does it.

that is how i approach mathematics. You need those to work out the details , not the 'big picture'.

@kremmen : the 'sigh' was not pointed at you.. it was pointed at the posts that started with "you need 'mathematics' and 'nuclear physics' and 'quantum mechanics' ... so we won't even bother to try to explain it, you wouldn't understand".

hFe , VceMax , IbMax et al are properties of a transistor that are determined purely by construction. hFe is balance between the depletion zones. Vcemax is how wide you can make the depletion zone ( wider isolation means you can hold higher voltage without flashtrough. IbMax is determined by thickness of the base layer and so on. This is stuff you can 'tack on' later.

Here is a nice one that i used to know the explanation for but i can't remember: if you reverse polarize the BE junction and you hit a roughly 6 volts threshold you will succeed in 'poisoning' the gate. This creates some kind of physical process whereby fre electrons become permanently trapped in the gate layer (i believe it is a kind of electromigration, but i can't remember exactly how it works) . the result is that the beta (hFE) permanently decreases. The longer you keep this up the lower the beta becomes. this goes on until the transistor is eventually destroyed. this process is irreversable. that is why in certain circuits you see actually two series diode ( or a zener) placed between base and emittor... this prevents this reverse voltage level from ever reaching the 'zener' voltage of the BE junction and causing this irreversible degradation.

my explanation is a base explanation. the finer details require much more work since you need to pull in physics , the atom model , chemistry ( because there are impurites during implant and deposition. no matter how good your mass selector is you are shooting hydrogen in that crystal. implantation also shatters the crystal structure and you need a healing process in an oven afterwards. the same process is used for 'drive-in' : get the implanted material to diffuse deeper. this causes a thicker layer. : thicker 'wire' = more electorn handling capability. More electrons per second = more amperes ..

Everything is interconnected in the universe like a ball of yarn , but you can only pick it apart by starting with the first thread. Saying 'it's a ball of yarn and very complex , you wouldn't understand' gets nobody anywhere. You need to actually sit down and begin somewhere.. too bad the fora are full of people that don't do this... this does not stop me from trying call me an idealist.

Besides, at the end .. you know how transistors are really designed ? By putting a bunch of geometries on mask, running the wafer in the selected technology process and then trying them out on a curve tracer. You run a bunch of corner lots ,burn them in a bit ,  plot some curves , look where the bell sits and you throw this in a library. presto. now you can go off and design something practical with these things. Slap in a spice model extracted from the plots and you can even simulate your design. Heck i have characterized once a full ibrary of transistors , even full opamps. We had all these variations. They were built , burned in and then sent through a test setup. I wrote the software that drove the current sources and swept them. i had a stack of keithley 2400 sourcemeters, some 34401 multimeters and a big multiplexer array. That hing spat out tons of curves. This was later crunched, overlap was removed and distinct 'transistors were selected. These geometries were then fully specced ( fT , destructive testing to see where they fried ) and later the spice model was built. This ended up in a design library and then we could make chips with that. it took months to build the design lib.
i made a testjig for the opamps where i could do cmrr psrr , bandwidth , unity gain bandwidth, gain. it took over  10 minutes to fully sweep one ( on different vcc's , temperature sweeps ) and we had thousands of those prototypes. i had 5 setups running in parallel with 3 techs ( the fab had 24/7 staff in in 3 shifts ). poor guys had to put a chip in the socket , close the metal box ( faraday cage) and press start. 8 hours non stop. week after week. We sent them a big box of bagels one day because we felt sorry for them

It is today STILL done that way. Whenever the process is scaled everything is re-characterized to build the design library. Companies that built 3 pin transisotrs also do this. We have a whole lab with 300 people that only does this. make variations, spin a wafer , select the best and then torture them.. I once saw  testing on one of those 'puck' thyristors destined for traction control (locomotives)... it was specced for 20 kiloampere... their task was to see when it would actually fry ... it violently exploded at about 35 kiloampere ... ( i was there to have a protection structure tested and analysed. it had failed and they needed to cut it up. The structure was supposed to withstand metallic discarge on phone lines but it failed one of the ISPRC tests. i was working on the analog frontend of ADSL modems at the time. was 1996 or so... long ago)

No designer builds transistors at the molecular level (unless you are a transistor designer.. ) you use what is in the 'pool'. Practical design is a collaboration and building on other subunits. There is no point in re-inventing the bloody wheel over and over. if i need a timer circuit i am not going to build a 555 by smelting and refining sand i found on the beach , and then try to construct a wafer etc ... i buy a 555 , read the datasheet and off you go. If you are tasked to design a timer that delays 10 seconds you don't need to be able to calculate the weak nuclar bond...
there is such a thing as 'practicality'.

anyway. just my two cents of trying to help answer questions that people have about electronics, in an understandable manner. the world is already full of questons on how to calculate anLED series resistor and hard-whino 'programmers'. I'm trying to 'lift' it a bit beyond that ,without spooking people too much... We live in a wonderous universe. Let's go out and explore !

@dave : that is a well know 'alternate' explanation.
If you read mine attentively you will see that i never use the word 'base current'. It is the voltage difference ( potential) that causes the electrons to flow , and the electrons are charge carriers. it i indeed the pressure ( the 'voltage' , technical definition 'potential' that cases charge to move ) i control the direction it is allowed to flow by applying pressure ( or void thereof ) to the base. i will get electrons out of the base ( or in the base-e) because there is a conductive pathway ( something that is NOT there in a mosfet. There is a connection in a J-Fet though, but we polarize it in reverse to create the barrier that way. ).

if you look at transistor plots , some do specify the vbe/Ibe plot.. just like you can make an Ib/Ic plot you could make a Vbe/Ic plot ... ( substitute the Ib scale with the Vbe/Ic plot.. and you got it.)
it is all interconnected. you can explain it in voltage domain or in current domain. for bipolars it makes more sense to explain it in current domain... for a mosfet it works better in voltage domain.
pure practicality...

[westfw]

MOSFETs are even easier to explain at a qualitative level.
The Source to Drain path is a "channel" that can contain current carriers (as per FreeElectron's "doping" description of silicon.)  A voltage (charge) on the gate sets up an electric field (Thus "Field Effect Transistor") can move those current carriers into and out of the channel, just because "like charges repel and opposite charges attract."

I vaguely recall my BSEE jumping pretty quickly from quantum mechanical explanations of theoretical transistors to measured properties of real transistors, without doing all the math needed to explain the exact behavior of real devices (and you look at the range of values permitted by a device spec sheet, and you realize that there are a LOT of complications in there.  Like FE says, it's all "layers" of understanding.

[Mechatrommer]

+2 bravo to free_electron... i just read about the section in academia book, pretty much thats exactly how he explained it. except i think (havent finish read it) free_electron got more details in the explanation. i hereby award free_electron with "nobel excellency in ee lecturacy" . i believe most people lost their way by thinking math describes everything... i believe math is built based on observation of the real world, not the other way around.

[M. András]

band gap references,

the explanation is on transistors , not bandgaps. if you want to study bandgaps you need to delve into chemistry(how the atom is built) and physics (how electrons interact with the nucleus of an atom)

why transistors perform so poorly when collector and emitter are interchanged

that is actually explained... has to do with the different doping strentgh between collector and emiitor. in a point contact or cat whicsker transistor there is no 'emitter and collector.. you find out which is which by TRYING it out... you can control how hard you press and where you create the better oping. only when planar transistors were invented and they performed the doping during deposition in the oven ( only later came ion implantation machines. i maintenacne on those beasties for a while. i actually started in the waferfab maintaining and repaireing the ion implanters and plasma etchers... that was fun. very clever technology like the mass analyzer to select what you implant , the dosimetry technique used. rotating magnetic fields to create uniform plasma dispersion )

thermal runaway,

has nothing to do with the fundamental working.
you are adding 'fuzz' to the basic operation. if you want to add fuzz : how about other impurities ? they create noise ? how about tunneling effects ? how about 'hot carrier injection ? . it does no good to

The mathematical model explains all of these exceptions without needing to resort to another analogy and having to explain why the analogy is no longer valid.

try to teach someone math by starting with integrating quadratic equation and see where you end up... nowhere.
Start with numbers and + - * / then work your way up. This is what i did here. Starting with the absolute basics.
Now you can explore if you want why electrons repel each other , how the recombination works on a physical level. Then you can add on what other dopants there are , when to use them andwhy. and then you can start looking at geometry of the electrodes. and you can pull in field theory and other stuff as well. But it does no good to start with a 500 page manual of equations.

Bravo, free_electron, an explanation without mathematics!

This is important, because if you think you need to resort to mathematical models to explain how something works, you don't really understand it. Mathematical models are used to calculate the details of what something does, not to explain how it does it.

that is how i approach mathematics. You need those to work out the details , not the 'big picture'.

@kremmen : the 'sigh' was not pointed at you.. it was pointed at the posts that started with "you need 'mathematics' and 'nuclear physics' and 'quantum mechanics' ... so we won't even bother to try to explain it, you wouldn't understand".

hFe , VceMax , IbMax et al are properties of a transistor that are determined purely by construction. hFe is balance between the depletion zones. Vcemax is how wide you can make the depletion zone ( wider isolation means you can hold higher voltage without flashtrough. IbMax is determined by thickness of the base layer and so on. This is stuff you can 'tack on' later.

Here is a nice one that i used to know the explanation for but i can't remember: if you reverse polarize the BE junction and you hit a rouglhy 6 volts threshold you will succeed in 'poisoning' the gate. This creates some kind of physical process whereby fre electrons become permanently trapped in the gate layer (i believe it is a kind of electromigration, but i can't remember exactly how it works) . the result is that the beta (hFE) permanently decreases. The longer you keep this up the lower the beta becomes. this goes on until the transistor is eventually destroyed. this process isirreversable. that is whay in certain circuits you see actually two series diode ( or a zener) placed between base and emittor... this prevents this reverse voltage level from ever reaching the 'zener' voltage of the BE junction and causing this irreversible degradation.

my explanation is a base explanation. the finer details require much more work since you need to pull in physics , the atom model , chemistry ( because there are impurites during implant and deposition. no matter how good your mass selector is you are shooting hydrogen in that crystal. implantation also shatters the crystal structure and you need a healing process in an oven afterwards. the same process is used for 'drive-in' : get the implanted material to diffuse deeper. this causes a thicker layer. : thicker 'wire' = more electorn handling capability. More electrons per second = more amperes ..

Everything is interconnected in the universe like a ball of yarn , but you can only pick it apart by starting with the first thread. Saying 'it's a ball of yarn and very complex , you wouldn't understand' gets nobody anywhere. You need to actually sit down and begin somewhere.. too bad the fora are full of people that don't do this... this does not stop me from trying call me an idealist.

Besides, at the end .. you know how transistors are really designed ? By putting a bunch of geometries on mask, running the wafer in the selected technology process and then trying them out on a curve tracer. You run a bunch of corner lots ,burn them in a bit ,  plot some curves , look where the bell sits and you throw this in a library. presto. now you can go off and design something practical with these things. Slap in a spice model extracted from the plots and you can even simulate your design. Heck i have characterized once a full ibrary of transistors , even full opamps. We had all these variations. They were built , burned in and then sent through a test setup. I wrote the software that drove the current sources and swept them. i had a stack of keithley 2400 sourcemeters, some 34401 multimeters and a big multiplexer array. That hing spat out tons of curves. This was later crunched, overlap was removed and distinct 'transistors were selected. These geometries were then fully specced ( fT , destructive testing to see where they fried ) and later the spice model was built. This ended up in a design library and then we could make chips with that. it took months to build the design lib.
i made a testjig for the opamps where i could do cmrr psrr , bandwidth , unity gain bandwidth, gain. it took over  10 minutes to fully sweep one ( on different vcc's , temperature sweeps ) and we had thousands of those prototypes. i had 5 setups running in parallel with 3 techs ( the fab had 24/7 staff in in 3 shifts ). poor guys had to put a chip in the socket , close the metal box ( faraday cage) and press start. 8 hours non stop. week after week. We sent them a big box of bagels one day because we felt sorry for them

It is today STILL done that way. Whenever the process is scaled everything is re-characterized to build the design library. Companies that built 3 pin transisotrs also do this. We have a whole lab with 300 people that only does this. make variations, spin a wafer , select the best and then torture them.. I once saw  testing on one of those 'puck' thyristors destined for traction control (locomotives)... it was specced for 20 kiloampere... their task was to see when it would actually fry ... it violently exploded at about 35 kiloampere ... ( i was there to have a protection structure tested and analysed. it had failed and they needed to cut it up. The structure was supposed to withstand metallic discarge on phone lines but it failed one of the ISPRC tests. i was working on the analog frontend of ADSL modems at the time. was 1996 or so... long ago)

No designer builds transistors at the molecular level (unless you are a transistor designer.. ) you use what is in the 'pool'. Practical design is a collaboration and building on other subunits. There is no point in re-inventing the bloody wheel over and over. if i need a timer circuit i am not going to build a 555 by smelting and refining sand i found on the beach , and then try to construct a wafer etc ... i buy a 555 , read the datasheet and off you go. If you are tasked to design a timer that delays 10 seconds you don't need to be able to calculate the weak nuclar bond...
there is such a thing as 'practicality'.

anyway. just my two cents of trying to help answer questions that people have about electronics, in an understandable manner. the world is already full of questons on how to calculate anLED series resistor and hard-whino 'programmers'. I'm trying to 'lift' it a bit beyond that ,without spooking people too much... We live in a wonderous universe. Let's go out and explore !

@dave : that is a well know 'alternate' explanation.
If you read mine attentively you will see that i never use the word 'base current'. It is the voltage difference ( potential) that causes the electrons to flow , and the electrons are charge carriers. it i indeed the pressure ( the 'voltage' , technical definition 'potential' that cases charge to move ) i control the direction it is allowed to flow by applying pressure ( or void thereof ) to the base. i will get electrons out of the base ( or in the base-e) because there is a conductive pathway ( something that is NOT there in a mosfet. There is a connection in a J-Fet though, but we polarize it in reverse to create the barrier that way. ).

if you look at transistor plots , some do specify the vbe/Ibe plot.. just like you can make an Ib/Ic plot you could make a Vbe/Ic plot ... ( substitute the Ib scale with the Vbe/Ic plot.. and you got it.)
it is all interconnected. you can explain it in voltage domain or in current domain. for bipolars it makes more sense to explain it in current domain... for a mosfet it works better in voltage domain.
pure practicality...

did you consider writing a book or teach at some schools? you would do fine

i always had problem in math, tons of unkown just letters without value or meaning, just solve that equation, what the hell for? it does nothing parctical the same equation with values or letters with assigned values were simple for me

[free_electron]

MOSFETs are even easier to explain at a qualitative level.
The Source to Drain path is a "channel" that can contain current carriers (as per FreeElectron's "doping" description of silicon.)  A voltage (charge) on the gate sets up an electric field (Thus "Field Effect Transistor") can move those current carriers into and out of the channel, just because "like charges repel and opposite charges attract."

Bingo ! You nailed it ! That's all there is to the working principle of a mosfet.

As for mathematics : they are just another modelling technique. One that can be very useful. But also one that can be very confusing. And, just like many modeling techniques is only as good as the detailedness of the model. Components today have so many properties that are still very hard to model or impractical. And nature doesn't give a hoot about the mathematics. You cannot go and yell at a component that it should behave as the numbers dictate.... That transistor will do as it pleases.. It is just a lump of 'stuff' where some interactions take place ... And you jump up and down and yell at it that it is not a 'nice transistor' because it doesn't follow your carefully calculated behaviour. If you are real lucky it will at least do something usefull. If you are unlucky it will violently commit suicide while jumping off the board and burying itself in the ceiling tiles, setting the rest of the building on fire...

I did a course at UCSC (university of california santa cruz) on signal integrity a while ago by one of the 'guru's in the field. He gave some examples using hyperlinx and some other tools and then he very quickly wrote that off. He gave an example to try to model crosstalk in a system. You have an agressor wire ( the wire carrying the'offending signal' that radiates energy ) and a susceptor wire ( the wire picking it up ).
These two wires run a complex path on a pcb with abunch of vias and layer hops.
They can extract the data from the real pcb layout , model it mathematically and run the numbers. Takes about a minute on a quadcore pc to get this nice color plot of the field strength and where the crosstalk happens...
Then the scenario changes... Three wires. Two agressors , one susceptor .. Calculation time : 30 minutes ...
Thee agressors one susceptor .... Just over 30 hours
Four agressors ?  Running on a Cray supercomputer ... 2 months and counting ... They had about half the plot ...
 At that point the instructor said. From now on we drop all mathematics , and we switch to an 'instinctive' approach.?. If you have 4 signals blasting energy in a 5th one .. You are a bad pcb designer and should not be making boards. You were lost 3 signals ago. It is pointless. If you have 4 agressors you let it run out of hand.... So there is no point in even trying to model that...

Let me add a few tidbits of extra information.. ( i believe i posted these in another topic but i can't remember ... Anyway .. Here we go )
Current handling capability : for a given thickness : make the channel wider and you can send more current through it. Dope it harder and its resistance becomes lower.
Voltage blocking capability (vdsmax) make the gate wider. Just like you would make a moat wider to prevent barbarians from jumping over them.

Vgsth ( threshold voltage to switch the mos on. ) this is controlled by doping and layer thickness. The thicker the layer is the more voltage you need to get on the gate. Simply because the field needs to penetrate deeper in the channel. The threshold voltage denotes when the mos is conducting but you dont use the full 'depth' of the channel yet. So thinner mosfets have lower Vt

The mosfet gate is a big fat capacitor formed by the gate electrode and the channel. There is an isolation barrier there that acts as dielectricum.

Ah now i remeber which topics. It was about flas memories and analog multiplexers. I'll go and search and post the links below

[A Hellene]

This is an excellent opportunity to clarify what Vgsth is all about, since it is a common misconception that the moment Vgs becomes equal to Vgs_th, the FET becomes fully conductive; which is far from reality! Actually, when Vgs == Vgs_th, the MOSFET begins to conduct, with its drain current Id just becoming measurable (250µA at room temperature, typically). From this point there is a long way until the device becomes fully conductive and decrease its Rds_on to the advertised levels, which will allow the drain-source voltage drop Vds to become the minimum possible, decreasing the amounts of power dissipated on the FET.

Assuming we are dealing with enhanced-mode N-channel MOSFETs used as switches (being turned fully ON and fully OFF), this is a selective quotation of a message I have posted somewhere else:


Without making things more difficult to understand (by introducing the switching model of the power MOSFET or the dv/dt induced breakdown due to the parasitic bipolar transistor model), the transfer characteristics of a FET are based on the charge quantity accumulated to the gate capacitance, in order to "open" the Channel and start the drain current Id flowing; and vice versa, based on the charge quantity removed from gate capacitance in order for the Channel to "close" and stop the drain current flow.

Now, the parasitic gate capacitance is not as simple as it sounds to be. There are three distinct capacitances in a MOSFET: The Cgs (the Gate-to-Source capacitance), the Cds (the Drain-to-Source one) and, most importantly, the Cgd (the Gate-to-Drain capacitance). The data sheets define them as follows, since this way the capacitances can be directly measured:
1. The Input Capacitance: Ciss = Cgs + Cgd
2. The Output Capacitance: Coss = Cds + Cgd
3. The Reverse Transfer Capacitance: Crss = Cgd

Only the capacitance Cgs is linear; Cgd and Cds are voltage depended. Additionally, Cgd is the most important parameter of them all because it is the main feedback element between the input and the output of the device. It is the capacitance charged with large magnitude voltage (Vdg = Vds-Vgs) charges capacitively coupled to the gate and actively resisting any Vgs level change. Cgd is known as the reverse transfer capacitance or the Miller Capacitance. Please search for the Miller Effect. It is sufficient to be said that the Miller effect is what predominantly limits the device's switching speed; especially in high speed switching of high voltage loads, where the Miller effect becomes a very considerable factor.

Another important parameter given at the MOSFET data sheets is the Gate Charge Qg that can also be broken down into the distinct charges of Qgs and Qgd, where Qg = Qgs + Qgd and it is the minimum charge required to switch the device on. Defining the gate element charges helps calculations; for example, a 10nC charge can be moved to Cgs in 10msec time by applying a Gate current of 1mA, and so on. Knowing also that Q=C*V, I=C*(dv/dt), etc., it becomes easy to calculate the current, voltage and timing elements needed for the Gate drivers.

A FET responds instantaneously to changes of the gate voltage Vgs. There are four Vgs regions during the device turn-on period and the goal is to raise Vgs to the final value (Vgs_driver) as fast as possible:
1. 0V <= Vgs < Vgs_th:
The FET is off, while the rising Vgs is charging Cgs: The Id is minimum and equal to the leakage current of the device; Vds is maximum. This is the FET turn-on delay.
2. Vgs_th <= Vgs < Vgs_Miller:
The device begins to conduct. This is the FET linear region, when Id is proportional to Vgs and Vds has not substantially been changed from Vds_off yet; Id = g*(Vgs-Vgs_th), so Vgs_Miller = Vgs_th + (Id/g).
3. Vgs = Vgs_Miller:
This is the Miller Plateau region of Vgs, where Vgs remains constant until the gate driver has adequately charged Cgs and discharged Cgd, while Id has reached its maximum value and remains constant, and Vds begins to fall.
4. Vgs_Miller < Vgs <= Vgs_driver:
This is the last step of the FET turn-on, where Cgs and Cgd have been charged to the final point, and the final value of Vgs now defines Rds_on and, thus, Vds and the device power dissipation. (For example, the NTD60N02R parametric Rds_on characterisation is: "Rds_on=11.2mohm for Vgs=4.5V and Rds_on=8.2mohm for Vgs=10V")

This is the relation between Vgs and Vds versus Qg, from the NTD60N02R data sheets:

Vgs and Vds versus Qg.png

The turn-off procedure of the FET is the exact backtracking of the turn-on steps, above. The goal here is the same: To turn the device off as quickly as possible. Again, to turn the device completely off will need to completely discharge Cgs by pulling Vg to Vss, while the hardest part will again be overcoming the Miller effect, where Cgd will oppose any Vgs change, trying to keep Vgs at the Miller plateau voltage region.


-George



EDIT: Image added

[free_electron]

correct. here is how i explain this stuff :

think of the channel as a valve. the harder you press the more water will flow. when you press on the gate ( apply voltage) water will begin flowing but not at full rate. for that you need to press harder.

Vgsth is the moment where you succeed in getting noticable conduction between source and drain. but you are not 'pressing' hard enough to have the entire channel be open.
The gate is at the surface of the mosfet construction with the channel underneath. this channel has a thickness.
when you get the mos to conduct (Vdsth) you are only using the area right at the top of this channel. if you apply higher voltage you succeed in opening the 'deeper' area's untl you can use the full thickness of the channel.
a thin channel ( think of a thin wire) has more resistance than a thick channel ( thick wire ) . in essence the gate voltage controls how thick of a wire you have between source and drain.

so for switching you want to get the thick wire as soon as possible... after all ohms law dictates that current times resistance gives voltage.. and voltage times current is 'power' or ... heat!

you frequently hear about 'mosfet drivers'... what are thoe then you ask.
Well the limiting factor is this darned gate capacitance ( and the other two ) . a typical i/o pin of a processor can only deliver a few tens of milliampere... so you have a problem there to charge or discharge this gate capacitor fast. ( remeber that you want to go into full conduction , or come out of it, as fast as possible to avoid losses...  ) And your i/o pin has a maximum 3.3 or 5 volt swing.
This is what a mosfet driver solves. it is an amplifier that can deliver high peak currents and peak voltages. this can charge the gate very fast and discarge it very fast.

Now, you have to be careful with that.. charging and discharging a capacitor is displacement of electrons ... displacement of electrons is current! So there is actually an AC current flowing in the gate when you are driving the mosfet from , lets say , a PWM source...

This causes dissipation in the gate !  This ac current will also couple, through those parasitic capacitors... and you get all sorts of nasty effects ...
so , sometimes you need a small series resistor between such a gate driver and the real gate. ( typically 22 to 47 ohms ) to dampen this a bit.

For very fast transients there exist even special ferrite beads you can slide over the gate pin of the actual transisotr before you solder it down.

[A Hellene]

This was a very nice analogy of the FET channel, as being a wire of variable thickness controlled by the gate!

Now, on the gate driving matter, I really regret I did not bother to capture the traces of the (rather fat) NTD60N02R gate in a low voltage (18V) SEPIC design, while I attempted to drive the FET directly by an AVR PWM output pin (with a true complimentary stage of Rds_on ~24ohm at Vdd=5V, for both the high and the low side output transistors) running at 64MHz. It was a surprise for me to see clearly at the gate trace the Miller plateau induced delay with Vgs clamped at Vgs_Miller, during both the gate charging and discharging phases! This was a real time Miller plateau visualisation, almost identical to the corresponding data sheets diagrams! In particular, when the FET load was connected Cgd was actively trying its best to oppose to any Vgs changes the AVR output line was struggling to make; with the load disconnected, thus with Cdg floating, I could only see the Cgs charging/discharging curves at the gate trace. Of course, adding a complementary emitter-follower stage gate driver using the BC639/BC640 matched pair and a 10ohn gate series resistor, the problem disappeared.


-George

[M. András]

so if i want to pass 40 volts trough the mosfet i need a gate drive voltage above that 5-15 volts whats the treshold voltage? i dont really understand this aspect of the mosfet or its independent from the voltage what i want to pass trough it, the driver chips even the analog ones can provide this?

[SeanB]

No, at 5V it will start to conduct, and at 15v it will be fully on, irrespective of the current in the channel. If you turn it on to the point where it conducts with 40V across it the voltage on the gate will be somewhere between 5 and 15V. At 15V it will generally be full on, with around a volt or less across it, depending on current causing a voltage drop across the Rds on resistance. The 40V will be the breakdown voltage of the device when it is off, ie the voltage above where it will break down.

[A Hellene]

so if i want to pass 40 volts trough the mosfet i need a gate drive voltage above that 5-15 volts whats the treshold voltage? i dont really understand this aspect of the mosfet or its independent from the voltage what i want to pass trough it, the driver chips even the analog ones can provide this?

Through a FET (or any other component) only current (which is flow of electrons) can pass. That is because voltage is the reason of current flow. Or, in other words, without a voltage difference (an electrical potential difference) there cannot be any current flow. Wikipedia will adequately cover and explain in sufficient detail all the terms I have just used.

Now, for every single component available, the manufacturers supply their customers with special literature called the data sheets that contain every little detail about the use of their components. To answer your question, you will typically need to apply a signal of +10..12V magnitude to a MOSFET gate in order to turn the MOSFET fully on; in most of the cases, a MOSFET gate can withstand no more than ±20V before it is destroyed.


-George

[free_electron]

here is the 'water' analogy :

'Voltage' is 'pressure'
'Current' is how many liters/second there flows.

For a given pipe thickness ( wire thickness / channel thickness ) and a fixed pressure you get x amount of water per second. increase the pressure (voltage) and the flow goes up (pipe thickness is constant).

The pipe thickness is resistance. The thicker the piper the lower the resistance....

Liters/ second = electrons / second.... electron/s = ampere ....
So a mosfet is actually a pipe where you control the thickness...
If you restrict the flow you create 'friction'... friction is heat ...

Now, there is a bit more about 'mosfets' that has not been told... in reality a mosfet does NOT have a drain or a source... It is the physical construction that 'creates' these.
A mosfet is really a resistor with a gate on top. just like a resistor has no designation for its electrodes , a mos does not have this.
All you need to do is 'lift' the gate 'x' amount of voltage above the channel. the current will automatically flow in the right direction.
In the physical mosfet there is actually a fourht terminal called the 'bulk'. we cannot leave that thing floating as there is a parasitic element that may pick up electrons and go conductive.. the mos would fail at that moment ( this 'parasite' is actually a bipolar transistor ). so we ( the people that make the mosfets ) tie this bulk to one end of the channel. this 'shorts' the b-e junction of the parasite and you are left with a diode. the location where the 'cathode' is connected we call the drain , the other one the source.

i will try to draw an a structural diagram that shows what is really happening there and how it is constructed. off to lunch now ...

[M. András]

sorry if i wasnt clear, i know only current can flow and coltage is just potential difference between 2 points, so the fet gate is starts to turn on lets say at +4 volt applied to it relative to ground in the circuit and it will be fully on at +15, but not much over that it will be destroyed? if i understand it right there is no connection to the voltage of the fet operates at lets say its in a 40volts circuit switches some load, and the voltage must be applied to the gate to turn it on or off, but i can vary its resistance by adjusting the voltage applied to the gate, i gonna get some next time i somewhere near an electronic component shop, i would hate to destroy any of the innoncent things jsut to figure out how do they work and how to use them

[free_electron]

wait for the drawing. then it will become clear.

[Legion]

Wow guys.  Great posts.  This is amazing!  Probably the best explanation of how transistors work that I've read.

[EEVblog]

Wow guys.  Great posts.  This is amazing!  Probably the best explanation of how transistors work that I've read.

Yep, I agree, this thread is just brilliant, well done to all!

Dave.

[free_electron]

Here is a bit of information on how they are constructed.. Let's see if i can remember all of this...

We start with a wafer of pure silicon. Silicon is a semiconductor element. This means that it can be made to conduct , or isolate depending on how you treat it , or apply voltages to it.
Wafers are available pre- doped with a donor or receptor material.
The silicon wafer is cut from a massive block of silicon that is pulled , much like you pull a candle from wax. They start with a furnace and put blocks of refined siliocn. They can add the dopant at this time.
The whole thing is heated in a blast furnace under a nitrogen atmosphere ( we don't want any oxygen in there as siliconoxide is a perfect isolator ... ) when the full thing is liquid we introduce a seed crystal.

Silicon, in its natural state is a crystalline structure , much like iron... A silicon atom wants to have 8 electrons on its outer shell but it has only 4. So it interlocks (shares) with electrons from neighbouring silicon atoms. This bond creates the crystalline structure.

The seed crystal is a tiny block of silicon that is a pure crystal. There are no cracks or irregularities in the crystal structure. It is no larger than the head of a pin...
It is fused to a carrier rod and clamped in the rotor. Assembly of a motor. This motor runs at a certain speed and spins the seed crystal around. The crystal structure is not put on its flat side , but under a slight angle ( i will explain later why we need this ) . Think of it as the tower of piza. Instead of having the atoms all perfectly next to each other in horizontal and vertical , we tilt the crystal under a slight angle.

Now, above this pool of liquid silicon we place a hollow tube in the shape of a donut and we pump coolant through it. The seed crystal is poked through the centre of the donut and placed on the surface of the liquid pool of silicon , as we spin it around slowly. At the surface intersection between the seed crystal and the liquid pool of silicon we succeed in melting a bit of the seed crystal.. Just a few atoms. Now we start ' pulling upwards through the hole in the donut. Since this is a cold zone the material solidifies there. We keep spinning around our axis while slowly moving upward as well. The end result is that we are growing a conical shape of silicon , starting from the seed crystal. Every layer of atoms that is added is in perfect alignment with the crystal structure of the seed crystal.

The 'donut' can actually expand. We can make this center hole bigger. This allows us to set the end diameter. For example a 4 inch rod , or a 6 inc or a 300mm rod. Once the 'cone' has reached the desired diameter we stop enlarging the donut , but we keep spinning the crystal and moving it in an upward motion. It takes a few days to grow the 'ingot' ( thats what we call such a rod of crystalline sillicon). They can be up to 2 meters long , 300 mm in diameter and weigh almost a ton. And ot is suspended from a tiny crystal that is only a few millimeter diameter.. The pull strength of silicon is fenomenal.

By far the largest producers of these silicon ingots are Dupont and Wacker. Those two combined do more than 90% of what is used.

This ingot is then cut usin a steel wire coated in diamond powder and polished to an extremely flat surface. The orientation of the crystal is marked by shaving off one side of the culinder. So the otherwise perfect round wafer has an flat region. We simply call this the 'flat'. Whenever process steps are done later they are aligned to this flat. You simply spin the wafer until it lands on the flattened portion and it stays there. The whole process of pulling a silicon ingot is called the Chrowalski method ( i hope i spell it right.. Polish name )

Right. Now we have a wafer of silicon. Off to the cleanroom with it.
The first thing we need to do is create doped regions. We can do this side by side , or we can stack them vertically. In 'the old days' and for some single transistor technologies we still construct vertically. To do this construction we need a pre-doped wafer. For horizontal construction ( called the planar process, because we work in one plane), like for integrated circuits, we do not use a pre- doped wafer.

Lets look first at the vertical process.
We have a wafer that is alread predoped. Lets say we start with an n- type doped wafer. The material has an excess of electrons ( free electrons ) because we introduced a donor material during the creation of the ingot.
We will put the wafers in a quartz carrier called a 'boat' and shove them in an oven. This oven is a long quartz pipe surrounded by very powerfull infrared heaters. We pump down the interior of this oven to vacuum and introduce a gas carrying silicon atoms. The carrier gas can be hydrogen or nitrogen. ) we also introduce a gas carrying a dopant material. We can play with the mix ratio to create stronger or weaker doped material ( remember my explanation of the transistor , the base is weaker doped than the collector).

The intense heat breaks the molecular bonds of the gases and the silicon atoms and dopant atoms fuse at the surface of the wafer. Temperature control is extremely critical... 1/100 of a degree c too much and the wafers melt and end up in a puddle in the floor of the oven, 1/100 too low and nothing happens...
 So we are steadily growing, on an atomic level , a layer of new material. The time we do this determines the thickness. Typical oven runtimes are 6 to 8 hours including temperature ramping...

Once we have grown this first layer. The wafer goes off to the photolitho room. Just like you make a printed circuit board , the wafer is coated with a photoresist and exposed to a negative image under a uv light source. There are a few peculiarities though... We don't use ( i always say 'we' because i work in this business. I started in a waferfab  19 years ago doing maintenance on these machines and now work in the design of the chips.. So i am familiar with how this stuff is all done in 'intimate' detail) don't use plastic film as a negative. The optical distortion is too high. The 'mask' is a quartz plate that has aluminum vapor deposited on it and engraved with either a laser or an ion mill ( a beam of ions is used to 'cut' and evaporate the alumium. )
This mask is not 1:1 scale but larger. Typically 1:40 ..
The quarts plate holds the image for a number of transistors side by side in a matrix arrangement.
The photoresist is exposed to this image using a lens system. Alignment is key and the machine that does this 'steps' over the wafer. That's why we call it a stepper. In the old days when geometries were big and wfers small we could actually expose in 1 shot. With todays large diameter wafers the distortion in the lens , and the size of the mask, becomes unusable, so we resort to stepping.
We also dont use normal ultraviolet light, but 'deep uv'.. This is typically made using an x-ray source that bombards a globe comtaining a gas. The reason is that, at the scale we work , the wavelength of UV is too large to go through the small openings in the mask in a 'clean' way... You create 'shadows'. The wavelength of regular uv is too large.
The power of these light source is also a tad brighter than you household pcb exposure unit... We need about 1/3 of a second exposre and we are done ...

Now, the photoresist is developed and unexposed regions are washed away ( we use negative process... As opposed to positive in home pcb making... )

Off to etching we go.
The areas not covered with photoresist will now be etched off. So we are now selectively removing part of our deposited layer... Two methods are in use. Wet etch and plasma etching.
Wet etch uses very nasty stuff like hydrogen fluoride and other chemicals to eat away the unwanted areas. Wet etch has a problem.. As geometries become smaller you get the problem that the liquid does not want to enter the little openings , or cannot be substantially refreshed to guarantee an even etch-rate all over the wafer. If you are familiar with etching you own pcb : some areas eat away fater than others. We cant have that... The geometries are too small and the risk of 'over etching is too large.. So, we switched years ago to a different technology : plasma etching...
We place the wafer in a pressure ( actually a vacuum ) vessel and pull a high vacuum. We introduce a reactant like silicontetrachloride or some other gas. The gas is inert and does nothing by itself... And themwe give it a swift kick in the pants by unleashing a few kilowatts of rf energy (13.56mhz industrial transmitters ) across it... This creates a plasma and rips the gas molucules apart. All of a sudden we get highly reactive atoms that start bonding with the material,we want to'eat away,. A continous stream of etching gas is injected while a big pump keeps extracting it. This plasma cloud is not uniform ...  It is a swirling soup of highly reactive elemnts.. To make it uniform we need.. A blender... Fortunately plasma reacts to magnetic fields. So we place two coils around this plasma chamber and send two 90 degree out of phase waveforms throught the,. This creates a spinning magnetic field that 'blends' the plasma cloud and creates a uniform reaction rate all over the wafer.

The etching precision is also much higher because we can pull another trick... When you etch a pcb you determin when to stop by looking if you can see through the board, or by time ..
Our structures are so small that this doesn't work .. And the wafer is not transparent. But we have another indicator. Plasma emits light... And the color of the light is determined by what materials are present in the plasma. So , we have a fiberoptic in the chamber that brings this light out, sends it through a prisma to break it in spectral lines and looks at the intensity of every wavelength present.
If we know we are etching silicon doped with phosphorous we look at the intensity of the 'phosphorous' spectral line. When all is gone ( we have etched through the layer and are now at the base of the wafer ) thie amplitude of this spectral line collapses ... Endpoint !
So these etchers actually employ a gas chromatography technique to find out when there is still stuff to eat , and when not... This gives a very precise etching method.

Right.. We now have a n type wafer with p type structures on top ... And a photoresistlayer... That has to come off.
When you make a pcb at home you now bring out the bottle of your wifes/girlfriends/own nail polish remover ( acetone) and you wipe it off.

We need a bit more precision... Averything needs to be absolutely clean...
So we use .. Strippers! No, not the pole-dancing type ... The technical name is an 'asher'.

Just like we used a plasma etcher to eat the unwanted material , we can use plasma to eat the photoresist. The 'etchant' this time is pure oxygen... We simply 'burn' it off in a plasma chamber. These machines are less advanced than real plasma etchers and simply use timed endpoints.
Although recently there are etchers that can do both. They etch first , when endpoint is detected they fully evacuate the chamber , switch to a different gas and eat the resist. The problem is that this does not work for all chemistries. The chamber walls need to be able to withstand both 'etchants'. Only etchers with amagnetical confinement field can do this as the magnetic field keeps the reactive plasma from touching the reactor wall and eating that one away too ...

Right. Now we have or second layer.. Well... Lets do it one more time. Back to the oven , deposit a layer of n material, slap some paint on it ( photoresist ) expose, develop , eat , wash and rinse.
Tadaaaa . A verical npn stack.
Now we have a tiny problem. Since the wafer we started with was doped .... All our transistors share a common electrode... This can be fine if you use a chip technology like rtl ( resistor transistor logic ... ) all emittors are tacked to a common ground there anyway... The trouble starts if you need a 'floating' transistor. For loose transistors you dont care either way. So lets first look at what happens if we were simply after making individual transistors that will packaged as a 3 pin device and sold as. A 2n2222 or b547 or whatever...

We need a way to fix the electrical connections. So we better put a mtal layer on top of our construction. Off to the sputtering machine we go...

Byq the way : this stack we made is not uniform... The bottom piece is wider than the middle pice which is wider than the top piece

Code: [Select]

     nnnn
   Pppppppp
 Nnnnnnnnnnnn

So now we will deposit a thin film of aluminum using a sputtering machine. The wafer is placed on a water cooled chuck and a bell is placed over this. In this bell sits a solid block of aluminum and a tungsten electrode. We pump down to vacuum , introduce an 'igniter' gas ( krypton, xenon ) and we strike a high voltage arc between electrode and aluminum block. This evaporates the aluminum and this cloud of gaseous aluminum lands on the cold wafer where it solidifies and grows a uniform layer of aluminum. Now, you have to remeber that our 'wafer' actually holds a 3d structure .. So this layer of aluminum is uniform in thickness, but it does follow the mountains and valleys on the surface of the wafer...

Layer thickness is given by time.

After this deposition we go back to lithography , apply another photo,ask, develop and back in the etcher where we remove the unwanted bits of aaluminum. Send it through the stripper one more time and.. Tadaaaa : a usable transistor.

Code: [Select]

    Aa
     Nnnn
   A nnnn a
   Pppppppp
A pppppppp a
 Nnnnnnnnnnnn
 Nnnnnnnnnnnn

So now we put our wafer in an adhesive rubber foil, bring out our dremel tool with diamond powder coated sawblade and we will cut up the wafer. The individual transistors stick to the rubber foil. The saw does not go through the rubber ( oscillating sawblade, like when they remove the cast around your broken leg. The blade only cuts hard stuff , not soft stuff )

Once we are done we stretch the rubber so the transistors separate ( this sawblade is extremely thin ... After all , anything we saw away is pure loss of silicon area... And the cost of a device is determined purely by its surface area...)

Amd now have a pick and place machine that picks a transistor 'die' off the rubber carrier , places it on a leadframe and friction welds it ...

Ah drat... I forgot a few steps ..

Back to the wafer wafter metal etching ,just before sawing....
The wafer is too thick .. We are fist going to grind the backside down in a wafer 'lapper' ( commonly called a 'disco'. Think about saturday night fever spinning balls ... Bingo. The wafers are spun aroundtheir axis while a counterrotating grindingdisk ( diamond dust... ) grinds off the backside.
The last thing we do is actually deposit another layer of aluminum, but this time on the backside of this thinned down wafer.

Off to cutting ..

Right the individual transistor is picked up and placed on the leadframe. The is a stamped preform of the three pins. Inside the transsitor the pins are terminated in little paddles with the emitter paddle being larger than the actual 'die'. I am talking packages like to92 sot 23 et all.. For metalcan packages like to39 to3 there is no leadframe.. We weld directly to the can.

The tool holding the transistor die is mounted on an ultrasonic piezoelement. So we can vinrate this transisotr wildly while pressing it down on the
Arge paddle of the leadframe, or the metal can. The friction melts the aluminum on the backside and presto : a welded transistor. And you have an instant emitter connection as well ( thats why metal cans are connected to the emitter .... ) of course you have a very thick emitter there so we add a bondwrie from the top emitter electrode to the leadframe or metal can as well to decrease resistance...

Some constructions do not use an aluminum backside but weld the die down with a silver glue. Isolated transistors insert a alumium oxide disk between metal can and die.. There are many ways to skin a cat here... Every manufacturer has his own way...

All that remains is jow to 'bond the two other electrode ( collector and base ) to their pins. In the old days we used gold , these days alumium, and for some specialty stuff also copper or still gold .
Bonding is also ultrasonic. Hold the wire , vibrate it so you get friction = heat . Wire diffuses intovdeposted aluminum electrode. Pull wire up and onto other connection point, repeat and cut.

Since the electrode on the transistor sivery small we ned to have a clean termination there. So advanced bondingmkachines actually pull an arc to the end of thee wire to create a nice round ball there. Think of itmas taking a piece of solder, heating the end so you get a little ball there ).

This guarantees a niece, precise shape and bond without risk of touching anything else. On the other side ( the paddle or pins) the structures are large and you don't need this.

Right so now we have made vertical transistors. ( point contact is older technology and skips the aluminumdeposition and bonding altogether. We simply poke two needles , one on gate and one on collector and use the mechanical pressure to hold the emittor in contact... )

Back to simple chips like rtl logic where all emitters are connected and all transistors are the same type. You can make a resistor using a piece of doped material. So these are made in the top n layer. The underlying p layer is shorted to the emittor to 'kill off' the transistor structure. You still have a diode between the tesistor channel and the substrated but this one sits reverse polarized and does nothingf.. Hmm thismmerits a drawing... Will have to wait until tomorrow.

To construct pnp transistors you could grow another layer of p material but you would also need an isolating layer. There were chips that were built this way but the yield was low and quality bad. Remeber this was early 60s and layer thickness control was not very good. Everything was experimental and everything was done by 'technicians' since there were no engineering courses in this stuff.. Funny isn't it ? All this stuff was invented by people without proper education ...

Right.. Now at one point some very clever people ( Robert Noyce , yes the guy that started intel , Jean Hoerni and a few others) came up with another idea.... The planar process. They had heard about a particle accelerator and thought.. What if we shoot dopants where we need them ? We can start with an undoped wafer and just blast donor and receptor impurites where we want them , in the right shape and with the right dosage ! The planar process was born.....

But that is a story that will have to wait until tomorrow...
I have to dig around in my garage. I have a box somehwere with masks, wafers, cut wafer on the runber foil, leadframes and tons of other stuff. I have a 15 minute video too that i made one day in the waferfab. We had an open-house day once and i got permission to film in the fab all the process steps. We showed this video at the entrance before the tour. It was filmed with a DV camera and i have it in DVD format somewhere.... I will need to get permission to release it... Should be doable. If i get permission i will upload it to youtube. It actually starts with sand refining , the pulling of the ingot and so on.

[PetrosA]

Excellent work! Thanks! It enables me to visualize how my Foveon sensors are made

[caroper]

It is amazing that something so complex can be sold for a couple of cents.
You have certainly put payed to any ideas of a DIY home Fab Lab
Great reading, you really should write a book.


Cheers
Chris

[IanB]

You have certainly put paid to any ideas of a DIY home Fab Lab

Well you can't make a useful transistor at home, but you can certainly make a functioning device as an educational experiment. Though apparently there are some practical details that may be a bit tricky to figure out.

[free_electron]

right. here's 'the second part'

so far i've covered 'the old way'. time to move on to a more practical manufacturing method : the planar process.
instead of stacking layers by growing them in oven , selectively eating them back off , growing another layer , eating it again and so on .. why don't we just deposit material where we want it ?

the photomask can't withstand the extreme temperatures in the oven .. finding a photoimaging chemical that can ... none found so far. so how can we get this thing accomplished ?

well , why don't we just shoot the dopants where we want them ? enter : the ion-implanter.
this is a big particle accelerator that can fire a beam of the selected material at the wafer. if we aim it right , under a slight angle so it can easier fly in the crystalline structure it'll lodge itself in the grid. the faster we make the material fly ( the more energy we give it ) the deeper we can shoot it... and the longer we expose the wfer to the beam the more ions we get in there.

wow. we can control not only the amount of doping ( remember we need weakly doped and heavily doped area's to make different parts of the transistor ) but we als need to be able to make thick areas to conduct large currents ... and that is depth control..
and since the machine does not care what it needs to fire .. we can shoot both donor and receptor material .. looks like a winner !

so how does this mythical machine work ?  very much like an old tv tube. with one difference : instead of firing electrons we fire ions...

In a long vacuum pipe ( this thing is 8 or 9 meters long ... ) at one end a heating element (tungsten) heats up to a very high temperature and is placed at a large negative voltage. we now introduce a carrier gas with the doping element of choice (fosfine , arsine , boron or antimony )

the high temperature breaks the molecular bonds and the intrdouced material falls apart in loose atoms. Now , about 10 centimeters away we place a round electrode with a hole in it. this is the extracting electrode. the negatively charge atoms ( ions) see this electrode and they go for it .. unfortunately for them , right behind his first electrode is a second one ... with an even higher potential... so they go through the hole towards this second one , which also has a hole in it .. and you guessed it . there is a third electrode . .by this time they are going so fast they don't defelct anymore , they just go faster .

now we have a bit of a problem. so far , we are just firing off watever we have ... hydrogen ( the carrier gas ) ,the dopant , bits of the tungsten filament .. we can't have that... so wee need a 'filter'. Enter : the mass analyzer.
we bend our vacuum pipe 90 degrees and we place a big electromagnet around this bend. And i mean BIG ... drive current : kiloamperes ..
Ions can be influenced by magnetic fields. The path of the light materials are bent very much, the path of the heavy materials very little.
as hydrogen is light , it is bent very sharply .. much sharper than 90 degrees and it hits the wall of the tube ... game over.
the heavy materials like tungsten are bent only slightly , so they cant make the 90 degree turn and hit the opposite wall. only the 'appropriate material can make a perfect 90 degree turn. This is why the tube needs to be so long... by playing with the magnetic field we make sure that only the selected ions make the correct 90 degree turn... any tiny little bit off and you end up in the tube all as opposed to flying out of the other side....
the magnetic field has slowed down the ions a bit so we throw in a couple more accelerator electrodes  and we pump up the speed to 120keV or 160 keV or sometimes more.
to bundle the beam we use an electronic 'lens' basically an electrode where apply a high voltage with the same sign as the ion charge. like charges repel. wo we can narrow the beam , or allow it to expand.

so now we have a very fast travelling beam of a particular ion. this beam carries a lot of energy and could destroy whatever structure we try to create. we also need a means to sweep the beam over the wafer surface.

We know ions are defelected by magnetic field. so we place two scanning magnets ( tow electromagnets under 90 degree angles ) and , much like old tv , we apply two sawtoothwaves , one for horizontal , one for vertical .. now to get rid of the charge .. you don't want that do disperse in your small structures .. you woudl fry them.. so we have a floodgun that floods opposite chare onto the beam just before it exits the tube. this neutralizes the electric charge and the ion reverts to being an atom ... chargeless and harmless, but flying very fast ... right against the surface of a wafer... in to it and permanently lodged where we wanted it.

and there oyu have it  : implantation of dopants !

Now, how do we do this selectively ? photomask ! the thcikness of normal fotomask turns out to be sufficient to trap the atoms.
where there is photomask the atoms are trapped and do not reach the wafer .. where there is no photoask they fly straight in.

so , just like we did in the old process we employ photomask. but this time a negative variant. in the oldprcess the mask protected the areas we wanted to keep after etching.
On the ion omplant process the mask protects the area's where we do NOT want the doping to take place.

wash , rince, repeat ..
the remainder is the same : metallisation has not changed.
the growing of oxide has not changed. ( oxide is used to construct the gates of the mosfets )
sometimes you need  nitride step , some steps are vapour deposition.

but you don't need all the deposit , etch , deposit etch steps. especially the dposit steps : they take a long time ( 7 to 8 hours in the oven ... )
and you get more precision ! nd its a lot faster. wafer exposure is in the order of minutes...

there is a little caveat though .. all this 'force' has a tendency to break the crystal structure a bit. And we can't really shoot very deep.. if we go too hard we would fly through the fotomask... so we need a bit of a post processing step called 'drive-in'
we throw the wafer in a hot oven and this 'heals' the crystal structure and allows the atome to 'settle' and 'sink-in'.

so yes, there is still a long run in the oven , but there is only one. we gain speed ,and we do not subject the wafer so many times to thermal stress ...

[M. András]

how can the leads of these fests handle those currents which some big fet claims? 2-500amps even to-247/264

[Kremmen]

Not to mention the bonding wires inside the package, connecting the silicon to the external leads.
Some tens of amps, maybe if the leads are cooled to the PCB tracks but hundreds - i don't think so.

[SeanB]

Normally multiple bond wires, or a foil strap. Just remember that a lot of these ratings are a pulse rating, and can be considerably larger than the DC ( or 100/120Hz as it will be effectively DC as far as bond wire heating is concerned) current in the datasheet.

[free_electron]

Not to mention the bonding wires inside the package, connecting the silicon to the external leads.
Some tens of amps, maybe if the leads are cooled to the PCB tracks but hundreds - i don't think so.

you can do 60 ampere on bondwires. a single bondwre if 1 mil thickness wil lhold 4 ampere without problems. put 14 or 15 in parallel and you are there...
those high current transistors sometimes employ double dies.

the cross section of a to247 pin can handle quite a lot of current. you cannot compare this to wire you put in the wall... the reason they restrict 20 ampere through a 2.5mm2 wire is because there is quite a bit of drop (long wire .. more ohms  ), there isolation around it and it sits in a confined space...
the to247 pin is bare metal...

a IXTV280N055T for example will do 280 ampere ... but look at the specifications of those pins ... that is a very fat pin ... and ... that 280 ampere is provided you can keep the junction at 25 degrees .... it's gonna be a short pulse at that rate ... your RMS current is going to be much much lower .... so yes , the pin will hold that.

other fets are made for direct bonding to an alox substrate and will go waaaaay beyond that

[SeanB]

OT, but a 0.5mm copper wire can do 30A plus, although it will act as a shantytown streetlight at that current. You can see some glow during the day as well, bare wire at chest height with earth return.

[free_electron]

ah, yes that's another trick. for high currents they don;t use aluminum bondwires anymore ... its copper and gold

[Technoguy3]

Thank you very much, free_electron. Out of reading countless explanations and watching videos on HOW transistors work, you just cleared it up for me in a matter of minutes.

Why does every engineer try to explain higher levels of abstraction first? I need to understand HOW something is physically working. If I don't, then I simply can't go further. It's why computer science instructors can't explain programming to me. They never want to explain what is physically happening. Just like math, electronics engineering should be taught from the bottom up, not the other way around. You can't expect a kindergartener to understand quadratic equations without first understanding the number system, counting, addition, and subtraction. I can neither understand quantum mechanics, electron spin, and equations for determining it, without first knowing what an electron is!

[IanB]

ah, yes that's another trick. for high currents they don;t use aluminum bondwires anymore ... its copper and gold

Ironically the main high current feed bringing electricity into my house has aluminium conductors. Perhaps they decided that copper wires with 100 A capacity were too expensive... 

[free_electron]

yep . they used aluminum wires for a while . cheaper than copper. but they stopped soing that... fire hazard. not in the cable itself but twhere the cable is terminated.
terminating unlike metals by pressure is a bad idea. making a gastight aluminum crimp is problematic. aluminu oxidizes very quickly and aluminum oxide is a reallky good isolator....
so you get contact resistance.. combine that with large current and ... P = I*I*R .... where P can be expressed in joules .... or heat ...

@technoguy3 : Mathematics is just one of the 'modeling' mechanisms at our disposal. some people, including me, are more visual oriented. I always liked how richard Feynman did it. As someone was explaining something he would make analogies in his mind. ah , this is a ball , no wait, two ball circling each other , one blue , one green . Now the green one grows hair ... and so on....
No point in beginning with massive equations. start simple and work your way up.

[T4P]

yep . they used aluminum wires for a while . cheaper than copper. but they stopped soing that... fire hazard. not in the cable itself but twhere the cable is terminated.
terminating unlike metals by pressure is a bad idea. making a gastight aluminum crimp is problematic. aluminu oxidizes very quickly and aluminum oxide is a reallky good isolator....
so you get contact resistance.. combine that with large current and ... P = I*I*R .... where P can be expressed in joules .... or heat ...

@technoguy3 : Mathematics is just one of the 'modeling' mechanisms at our disposal. some people, including me, are more visual oriented. I always liked how richard Feynman did it. As someone was explaining something he would make analogies in his mind. ah , this is a ball , no wait, two ball circling each other , one blue , one green . Now the green one grows hair ... and so on....
No point in beginning with massive equations. start simple and work your way up.

I am still baffled and wondering why the A380 has been wired using aluminium wires ... EH?!

[SeanB]

Aircraft electrician is generally a much better trained and more careful worker. That means the cabling can be prepared properly for termination, and the connectors will be a much more expensive alloy that is less likely to corrode in contact with the aluminium. Plus the regular maintenance cycle and the connectors being designed to keep the contact areas dry and sealed does help.

That will probably reduce the wiring loom mass by a good few tons, even if it does increase the maintenance cost slightly and requires a special training cycle for the maintenance staff over what they already have.

Aircraft wiring is easy, 1 million wires in looms, all white, and all identified by illegible markers applied every 30cm along the wire. On the plus side the looms are often available in sections for easy changing if they are faulty, and there are plenty of plugs and sockets in it. Bad is some are make in situ due to clearances, and you need an extra elbow to do it easily.

[Kremmen]

yep . they used aluminum wires for a while . cheaper than copper. but they stopped soing that... fire hazard. not in the cable itself but twhere the cable is terminated.
terminating unlike metals by pressure is a bad idea. making a gastight aluminum crimp is problematic. aluminu oxidizes very quickly and aluminum oxide is a reallky good isolator....
so you get contact resistance.. combine that with large current and ... P = I*I*R .... where P can be expressed in joules .... or heat ...
[...]

They still do, at least around here low voltage powerline cabling (3 phase 400V supply) is done with aluminium as a rule.
The termination issue is true and it did cause problems until it was acknowledged that you just can't connect aluminium like you do copper. What is now done is that splicing and connecting to copper is done using a special spring-loaded clamp connectors with a hermetic aluminium-copper inteface where needed, and using a special grease to remove the oxide and protect the connecting aluminium surfaces. The spring tension takes care of the tendency of aluminium to creep and loosen the joint. This and oxidation created the fire hazard.
Properly done it works without problems. And at least around here the licensed electricians are well trained to understand the risks involved in aluminium cabling. I haven't seen reported problems and i am sure there are none.

[free_electron]

I am still baffled and wondering why the A380 has been wired using aluminium wires ... EH?!

aircraft is NOT house cabling !. they use aluminum simply because of weight !
They won't use crimp connections eather in aricrafts , and neither will they simply put a wire under whatever screw and tighten it...
they will probably weld the cable to an end lug and then put that under a gas-tight clamp plate.

And, as kremmen said : they'll apply some for of surface protectant.

The US and Canada did an experiment to use aluminum wiring in houses in the 80's.. now it is illegal to do this. simply becasue they had too many fires...
here is some reading material on the how and why : http://en.wikipedia.org/wiki/Aluminum_wire

[T4P]

I am still baffled and wondering why the A380 has been wired using aluminium wires ... EH?!

aircraft is NOT house cabling !. they use aluminum simply because of weight !
They won't use crimp connections eather in aricrafts , and neither will they simply put a wire under whatever screw and tighten it...
they will probably weld the cable to an end lug and then put that under a gas-tight clamp plate.

And, as kremmen said : they'll apply some for of surface protectant.

The US and Canada did an experiment to use aluminum wiring in houses in the 80's.. now it is illegal to do this. simply becasue they had too many fires...
here is some reading material on the how and why : http://en.wikipedia.org/wiki/Aluminum_wire

Right, thanks for clearing up. I forgot some things at a spur of the moment.

[M. András]

off
hahh, 3 years ago we still had aluminium wires in our home, till i replaced it with 2.5mm copper wires, dear god<- the only 1 word left my mouth when i removed the plastic cover of the breaker box 5 black wire 2 large diamater one 1 bigger then the other, 3 single 240volt wire, if i would dare to rewire it i would have a 3 phase connector, the horror continued, null/return+ground connections separeatly twisted to the larger diameter wire with burnt insulation and electrical tape from the 80s, replaced the breakers too.
off

[marcosgildavid]

Hi,
take a look at:

http://mosfet.isu.edu/classes/stout/EE%20329/

Chapter 5

There are some really good information in this docs, I've used them to study for my electronics course.

Hope it helps.

[cabraham]

http://amasci.com/amateur/transis.html

Don't let anyone tell you they are current controlled

Every bjt maker says they are current controlled, at least at the big picture viewpoint.  At the micro level, charge control models are employed.  I has a long exchange with Bill, the keeper of the web site you referenced.  I'll dig it up and provide a link later tonight.  Best regards.

Claude