SEEED pcbs /\/\ 2nd batch !

[3roomlab]

the 12mil vias do seem like a challenge dont they?

are 12mil vias a terrible thing to do on most PCBs? or most vias should be done larger? 15mil? 20mil?

this is a 0.6mm 2 layer 1oz pcb

[wraper]

If you expected all vias to be evenly filled, you should pay for plugged vias additionally.

[3roomlab]

i see .... thanks for that info. something new
http://www.pcbuniverse.com/pcbu-tech-tips.php?a=5

[T3sl4co1l]

Referring to the barrel finish or anything, or just the sporadic tenting?  If you're tenting vias, surely you're expecting it to be plugged at least part of the time, no?

Also, speaking of, it would be interesting to see a true cross section and micrograph of some of these boards.  See how they really work out in construction quality.

Tim

[3roomlab]

i didnt request for any special via "treatment" and the only form of via treatment i heard of before i submitted this pcb is tenting, and i thought there is only the mask tenting lol

so im guessing this is a random effect of the masks stuff going in or not.

yes indeed i am quite curious how the section will look like esp how well the via plating is done inside (more so, im interested to discover how well more a 0.6mm PCB can pass heat) ... but i do not have any nice cutting tool nor high powered magnifier with ccds ... who wants a go at it? i dont think i will be using any of these 10 pieces because i am very sure i have done the SOT223 vias wrongly and the SOT223 will overheat and protest very angrily ! ( all my vias are around it ... but none are under or inside the pad ha ! otherwise, it could perhaps handle very low LM317 loads with the power PNP, there are also other very exciting noob mistakes on this pcb lol)

[wraper]

Generally it is better to remove silkscreen around vias. The reason is that chemical contamination might be entrapped in the hole which can cause corrosion in the via later.

[wraper]

On the second PCB photo vias don't seem to be simply tented but filled indeed.

[wraper]

i dont think i will be using any of these 10 pieces because i am very sure i have done the SOT223 vias wrongly and the SOT223 will overheat and protest very angrily ! ( all my vias are around it ... but none are under or inside the pad ha ! otherwise, it could perhaps handle very low LM317 loads with the power PNP, there are also other very exciting noob mistakes on this pcb lol)

Generally you shouldn't do vias in the pad itself as they will suck solder into them what could cause serious soldering issues.

[westfw]

"filled" vias means filled with solder (perhaps during solder plating, perhaps during assembly), right?
"tented" means that the soldermask is coated over the holes, and I'd expect whether the holes get filled with mask material to be somewhat random.

From the photo in the 2nd message, NONE of your vias is bare of soldermask.  Are these from EAGLE?  Eagle has a parameter where only vias larger than a certain drill size are bare.  For heatsinks, you'd want your vias un-tented, and perhaps with the entire heatsink bare (which you'd have to do by manually editing the soldermask layer.)  Ideally, I think the holes should be filled with solder for better heat conduction.  (easy enough to do manually; I'm not sure about reflow or paste...)

[T3sl4co1l]

i dont think i will be using any of these 10 pieces because i am very sure i have done the SOT223 vias wrongly and the SOT223 will overheat and protest very angrily ! ( all my vias are around it ... but none are under or inside the pad ha ! otherwise, it could perhaps handle very low LM317 loads with the power PNP, there are also other very exciting noob mistakes on this pcb lol)

Generally you shouldn't do vias in the pad itself as they will suck solder into them what could cause serious soldering issues.

Yeah, better to avoid, but used responsibly, it's not as big a deal as it sounds.  It's most critical for small pads that don't have any solder to spare.  You want to avoid via-in-pad for e.g. gull-wing (SOIC or finer, not that you can get a to-spec via inside anything finer pitch), QFN (side), LGA, etc.  BGA aren't as big a deal (there's a whole big ball of solder to spare!), but are preferred to be done with "dogbone" connections.  I'd say... it can be done for e.g. larger chip resistors/capacitors, but still best avoided.

It's least critical for large pads with lots of solder to spare (e.g., SOT and DPAK power tabs?), and a non-issue for hand soldering (likely for amateur projects).

QFN (and others') exposed pads are normally designed to use less than 100% paste coverage, so you can kick it up to 100% and add a few vias, anticipating that the vias will wick the excess.  I think preferred is to use solid or plugged types, but these are more expensive, and unplugged vias are second best.  (Tented vias are least preferred, because tenting inevitably traps gas that causes solder voiding.)

Very thin vias (generally 12 mil and below) are thin enough that 1. they don't soak up much anyway, and 2. they don't often soak to begin with -- especially on RoHS processes, it seems, solder doesn't flow into small vias.  This is another reason small diameter vias are preferred around fine pitch stuff.

Tim

[3roomlab]

yea im hand soldering, and i am assuming i can fill in as much solder as i can feed it. and the idea is to use many vias to negate the PCB purportedly high ^oC/w, so it will be as "transparent" as possible passing heat onto the backing heatsink.

i cant remember who gave me the hint that i could increase the via hole size, and today i went back to this "calculator" (http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/) ... and a bigger hole size seems like a good idea

@ 31.5mils (0.8mm hole)
ampacity is @ 2A+
thermal resistance @ 46^oC/w
assuming 0.6mm PCB + 0.5mil via plating

next pcb will try bigger vias
maybe this time, the mask will not "accidently" flow into the holes

thanks for all the tips folks ! 

[T3sl4co1l]

Heck, if you really want to go for it, use 20-30 mil vias, no tenting, so they'll soak up like a moist towel.  And solder the heatsink directly onto the backside, e.g. with a copper heat spreader.  The solder plugged vias will easily conduct much more than the thin copper walls.  Might even be able to get up to 20W out of it.

Tim

[3roomlab]

Heck, if you really want to go for it, use 20-30 mil vias, no tenting, so they'll soak up like a moist towel.  And solder the heatsink directly onto the backside, e.g. with a copper heat spreader.  The solder plugged vias will easily conduct much more than the thin copper walls.  Might even be able to get up to 20W out of it.

Tim

indeed, will be trying this out on next chunk of PCB

and this via ulp, tried it, can be used to fill alot of annoying vias !
ftp://ftp.cadsoft.de/eagle/userfiles/ulp/via-fill.ulp

[3roomlab]

just to try out some ...
this version is using the SMD to heatsink idea (via a brass tab interface)
and yes, i dont have any SMD caps on hand yet

still, on calculator, a direct brass tab do make the thermal path seem the better way to sink heat

... and the PNP died soon after LOL

[3roomlab]

batch 2 from seeed ...

of the 20 pieces, 2 units seems to have a small chunk of PCB eaten by a tiny cartoon dog

[3roomlab]

the "dog" bite
and a tiny pad for TSDSON8 3x3 !

[SeanB]

Probably was the registration mark for the panel, so your board will have very good alignment of all the layers, masking and screen printing.

[3roomlab]

lol i think they ran out of 0.6mm PCB and used something that was slightly damaged. nope i didnt make any reg marks.

anyway, the power supply board works nicely
using a VR, the PMOS variable current limit is successful ... YAY !

and now i think i will try to change the circuit into something ... to handle even more heat