Better to check on source termination, and verify any edges you need.
The 6502, is that CMOS or NMOS, and how strong are the output drivers? NMOS of that era, I believe, was usually 5V supply, TTL compatible, with a fairly low fanout. And CMOS was symmetrical drive (inputs might not be TTL compatible, outputs meet/exceed TTL spec), but also quite weak.
If you want to put that on an extensive bus (like a card cage), you'll have to use bus drivers / transceivers, using bus signals to drive them appropriately. The bus state signals themselves will need to be buffered of course, which may be a challenge if you want to include multi-master modes. (The usual solution is to use open-collector signals.)
I wouldn't recommend using anything faster than 74HC(T). You're only inviting trouble if you use AC, F, ALS, etc. Most of the value will be wasted, anyway, because you'll probably need to series-terminate their extra-strong outputs. HC is about right with an extra 33 ohms in series, given the impedance of most traces.
For layout, you'll preferably want 4 layer build, with outer layer traces around 100 ohms (typically 6-7 mil width over 10 mil prepreg). Since that costs extra, you might stick with 2 layer, in which case, try to route as much bus as possible over solid ground plane. Use somewhat heavier traces (10-20 mil), with similar or greater spacing to reduce crosstalk, and make bus crossings as well grounded as possible (when crossing a bus on one layer, try to surround single traces (or no more than a few abreast) with ground plane on the opposite layer, well stitched to the surrounding ground on both sides).
When using ribbon cable, ground every other trace. The impedance of any given pair of wires is about 120 ohms (differential), and one wire against two neighboring grounds is about 50 ohms. You'll probably want to use bus drivers in front of such a cable, since it won't match to system impedance (i.e., ~100 ohms). You definitely don't want to run an entire bus in adjacent wires, because that 120 ohm figure becomes coupling and crosstalk between neighboring wires -- sure to make a mess.
You can minimize or avoid a lot of trouble if you allow enough time for signals to settle before the strobe events occur. Typically, this is already provided, so the CPU (or other device) asserts an address (and optionally, data), then some clock states later, asserts the bus strobe (RD, WR, IO, direction, whatever). If you have any edge-triggered devices, you need to make sure the strobe is very clean (this is a big gotcha for newbies to SPI, which depends critically upon the clock signal). You can relax it a bit if devices are asynchronous and level-triggered only (e.g., using 74HC373s over 273/374s), so that the address/data stays stable during the strobe (which might be multiple strobes due to bounce, but it doesn't matter).
You also want to have twice the total bus length (end to end and back again) less than a clock half period. Figure speed of light about 0.67c (in PCB, coax, ribbon, etc.). Close enough. This is the most powerful consideration, because at the low clock rates old machines ran at, you can simply have ribbon cable piled out of the bus and not really care, even with the impedance mismatch.
Tim
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