Maybe this will help:
http://www.ecircuitcenter.com/Circuits/op_ibias/op_ibias.htm
Read the article, thank you a lot! So Ios = Ib+ - Ib-, yeah I studied in the degree that these bias currents are different, but always neglected their effect, as they are usually of the same order of magnitude. I'll try to play with the values later ahead.
The param :- Average input bias current ~ This is the small current that the Op Amp sinks/sources from it's input pins. It is defined as (I non inv + I inv) / 2 .
Due to this if you feed the Op's inputs from very different impedances you will create an unwanted offset voltage when this bias current flows through these different impedances. So try to keep the input impedance of the input circuitry the same on both inputs and the offset voltages will tend to cancel out.
Bias Input Offset current:- is the difference in bias current between the input pins. Now a lot of newer op-amps (like 0p07 op27 series) are designed with input bias current cancellation. For these parts the input bias current is a very low and temp stable and the input bias offset current in these devices is nearly equil in size to the input bias current (thats how you can tell if Op is using internal bias cancelation) . When these two params are nearly equal in magnitude you should not use impedance equalizing resistors in these opamps as you can end up making the offset current effects worse than the average input bias current effects.
Here's a link, note page 3 in particular :- http://www.analog.com/media/en/training-seminars/tutorials/MT-038.pdf
Regards
What do you mean by input impedances? As far as I've been taught the chip has a given input impedance which is increased by the closed loop gain. So those input pins have actually different impedances?
Saludos!
I've been doing some projects with a TL081 op-amp, as these are quite sensitive to errors I have a good track about theoretical real values like the offset voltage and the input bias currents. However after taking a closer look at the datasheet I've noticed an additional paramenter "Input offset current", at first sight I though "well, it is probably the offset voltage divided by the input impedance since it is so small" but I am not sure about this. I've reaserched on the forum and on the internet but I don't find any clarification on the matter. I would be very thankful if anyone could explain me what is it.
Thank you for your time,
Alex.
Why are you using the TL081?
Do you have very high input impedances?
Unless the impedances imbalance at the inputs are over 10M, or the IC is very hot, the voltage offset will be much greater than the offset due to the bias currents, even if the offset current is ignored.
Worst case figures for the TL081 @25oC:
VOFFSET = 15mV = 15×10-3
IBIAS = 400pA = 400×10-12
Source: data sheet
http://www.ti.com/lit/ds/symlink/tl084.pdf
Calculate the input impedance imbalance would be required to create a voltage difference of 15mV
R = VOFFSET/IBIAS = (15×10-3)/(400×10-12) = 37.5×106 = 37.5MOhms
If you're having problems with the offset, it's most likely because, being a JFET amplifier, the TL081 has a poor input offset voltage specification. Try changing to the OP07.
Well, the TL081 is cheap here (and ine of the few Op-amps I can get with ease), actually the offset voltage is of no concern to me(SW and GBW are the main parameters I take into account), I'm just interested in the AC part of the signal (I just plug a coupling cap), but I was curious how that might affect the output, it is nice to know what would happen to the design at any stage and frequency.
As I have understood that would be the imbalance between the inverting input and non-inverting input impedaces, isn't it?
Thank you for your replies!