internal power rails for DIY power supply

[exe]

Hi guys,

I'm designing a power supply. Internally it needs +20V,  -5V (for opamps), +3.3Vdigital, +3.3Vanalog rails (for MCU). Analog rail is used for STM32's DAC and ADC.

Questions:

1) Can I join 3.3V rails together? Or digital noise will get through, even if I add an RC-filter to DAC output?

2) My 3.3V reference (ADR4533) accepts maximum 16V, but I have ~20V unregulated. What should I do to supply ADR4533 from 20V? Can I add a (linear) pre-regulator? Can this potentially affect stability? (I heard chaining regulators is not the best idea). Can I supply two ADR4533 from the same pre-regulator?

[danadak]

1) Can I join 3.3V rails together? Or digital noise will get through, even if I add an RC-filter to DAC output?

Join the Rails at the source, do not chain (serialize) the loads on a single buss. Same can
be said of the grounds. In fact consider using chip Ls at source to each 3.3 V buss to
generate isolation between busses.


http://www.analog.com/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter12.pdf

https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100

http://www.cypress.com/documentation/application-notes/an57821-psoc-3-psoc-4-and-psoc-5lp-mixed-signal-circuit-board-layout

2) My 3.3V reference (ADR4533) accepts maximum 16V, but I have ~20V unregulated. What should I do to supply ADR4533 from 20V? Can I add a (linear) pre-regulator? Can this potentially affect stability? (I heard chaining regulators is not the best idea). Can I supply two ADR4533 from the same pre-regulator?

Yes I would use a pre-regulator or a zener to affect the drop, latter cheaper and easier.
Chaining regulator could affect stability, load dependent, Capacitor ESR issues and what
regulator gets what cap. Cap dump problems during power off. Try siming this, but I suspect
models may not be adequate. You can do real time scope review looking for transient that
convey phase margin is compromised, eg. lots of ringing.

391 OpAmp CM range includes ground, any chance there is ground rail bounce such that
the <= -.3V limit exceeded ? That could cause comparator phase reversal.  Your DSO
can look at that. Use DSO in differential mode, see ap notes below.


https://www.njr.com/semicon/design_support/faq/10088.html

http://www.analog.com/media/en/training-seminars/tutorials/MT-036.pdf


DSO differential / floating measurements (safety first) -


http://download.tek.com/document/51W_10640_1.pdf


http://www.newark.com/pdfs/techarticles/tektronix/FFM.pdf


https://www.tiepie.com/en/classroom/Measurement_basics/DifferentialMeasurements


https://www.google.com/search?ei=NygxWsq9L4Sl_QbLzp6oDQ&q=differntial+scope+measurments+tektronix&oq=differntial+scope+measurments+tektronix&gs_l=psy-ab.3...1825.4725.0.5264.12.12.0.0.0.0.98.886.11.11.0....0...1c.1.64.psy-ab..1.8.654...0i13i30k1j0i8i13i30k1j33i160k1j33i21k1.0.fB4yRdrzC90




Regards, Dana.

[exe]

Thank you, Dana, for detailed response. I'm digesting all the information you provided...

One quick question: did you mean connecting zener in parallel or in series with the regulator? (I assume in series on the high side).

[David Hess]

1) Can I join 3.3V rails together? Or digital noise will get through, even if I add an RC-filter to DAC output?

An RC or LCR filter may allow this however ground considerations are likely to cause just as much if not more of a problem unless a careful layout is used.

2) My 3.3V reference (ADR4533) accepts maximum 16V, but I have ~20V unregulated. What should I do to supply ADR4533 from 20V? Can I add a (linear) pre-regulator? Can this potentially affect stability? (I heard chaining regulators is not the best idea). Can I supply two ADR4533 from the same pre-regulator?

Practically any preregulator would work fine including a resistor and zener diode shunt regulator.  Or a JFET or other cascode circuit could be used to control the input voltage to the reference from the output voltage.  Depending on the range of the unregulated voltage, a series zener diode is another possibility depending on how good the line regulation of the reference is.