Is using only 10 pins on an ARM/FPGA considered a sin?

[SolarSunrise]

This might be a stupid question but here it goes:

In my projects I need a lot of computing horse power (primarily FFT and wavelet transform analysis) therefore I have been using STM32F4's quite extensively. Since the ADC's in these chips are not very precise, I used an external 24 bit ADC to capture data. So in total, out of 80 available GPIO pins, I have only used 10 GPIO's. That includes SPI, LCD bit bang, and other miscellaneous odd and ends.

It just occurred to me that this might be a sin: using only 10 pins out of 80 pins. Is this considered a waste? A bad design practice?

Thanks in advance!

[Simon]

Is it the most efficient way of achieving what you need to achieve ? if so then no.

[c4757p]

Do you pay by the pin?

Some of the most powerful FPGAs have hundreds to over a thousand pins. Do you think they are always all used?

[Simon]

How many arduino projects are there using just 2 I/O pins ? 

[electronics man]

Do you pay by the pin?

Some of the most powerful FPGAs have hundreds to over a thousand pins. Do you think they are always all used?

I wish they could make small (dip 40) FPGAs not many pins but still the same horse power

[krivx]

DIP is a very small market. There are CPLDs in 44 pin PLCCs and QFPs, Altera do the MAX 3000 range.

[SeanB]

It costs less to make a BGA package with 200 pins than a 40 pin DIP, just in the cost of the material used. As well it uses less board space, packs denser in shipping and costs less to ship. So the manufacturers will only do a 20 pin package if you order 100k units and are willing to pay for the special packaging of it. You will most likely get these as a 12-16 layer board with a bump chip on it in a blob pack, and the multilayer board will be used to bring the pins out along with having the supply decoupling caps on it. You can see this in some of the meters Dave has torn down where they have a classic 7106 layout with a separate COB board with a blobbed chip on top to get the DIP40 package. It must have gotten to the point where a COB board is cheaper than a DIP leadframe in kovar.

[nerdyHippy]

I'll cut your the unused pins off your chip for a small fee.

[miguelvp]

I'll cut your the unused pins off your chip for a small fee.

Don't know about that, might cost a lot of time to cut off those unused pins off!

[codeboy2k]

I've often thought I'd like a high LE count with low pin counts... say power/ground/IOVCC1/IOVCC2 for 2 IO banks and 4 pairs of SERDES in a 12 pin BGA package. I want the small size, with large LE's... but I think a die that small won't actually have enough room for the IO banks and the large number of LE's, plus the routing fabric.. I just think the die will be too big.. and that's why they always release it in large pin count BGAs

Maybe at 14nm it can get better.  Maybe if they ever want to release a smaller package with high LE's they will stack multiple dies vertically. This might actually improve the routability and decrease p_d

[EEVblog]

No. It's very common in the industry to use huge pin count FPGA's (to get the LE's required) and do nothing but high speed serial decoding/encoding using on ly a fraction of the available pins.

[Kjelt]

Don't know exactly what you are doing but your description "primarily FFT and wavelet transform analysis" and the use of ADC's suggests to me that you use and need the DSP part of the Cortex M4 core?
So then it seems a good choice unless you can find cheaper more powerfull other brands that can do a better job. Still that is not relevant for your question, so I agree with the above: use what you know, can get and works.

[miguelvp]

FFT and Wavelet transforms can be done with parallel computing. Sequential (even DSP) won't be as quick, so FPGA's make sense. But GPU's and OpenCL might be a bit better at it (maybe), although there is OpenCL for FPGA's as well.

The Arm processor might be used for coordinating and setting up the sequential portions of his project. Any micro might do for that task, but since now they have SoC embedded in FPGA's makes sense to use it that way.

[SolarSunrise]

Do you pay by the pin?

Some of the most powerful FPGAs have hundreds to over a thousand pins. Do you think they are always all used?

As you may know, you can't find powerful FPGA's/ARM's with low pin counts... And if there is any, I found that they sometimes cost more than a 100 pin LQFP...

Don't know exactly what you are doing but your description "primarily FFT and wavelet transform analysis" and the use of ADC's suggests to me that you use and need the DSP part of the Cortex M4 core?
So then it seems a good choice unless you can find cheaper more powerfull other brands that can do a better job. Still that is not relevant for your question, so I agree with the above: use what you know, can get and works.

Yes that's correct. I have considered using DSP's but I am also incorporating radio transmitter modules along with LCD displays. And since I have used a lot of Cortex series processors before, I don't have to start from scratch. Heck, STM32F4 DSP functions are pretty powerful, comparable to some of the DSP's out there so why not use it?

No. It's very common in the industry to use huge pin count FPGA's (to get the LE's required) and do nothing but high speed serial decoding/encoding using on ly a fraction of the available pins.

Well, that comment alone, coming from an experienced engineer, marks the the thread as solved  Thanks Dave! Learning new stuff everyday here, since I'm not an electronic engineer.

[codeboy2k]

No. It's very common in the industry to use huge pin count FPGA's (to get the LE's required) and do nothing but high speed serial decoding/encoding using on ly a fraction of the available pins.

Yep.  I'm always doing that.. and just using a few diff pairs for SERDES in and out, maybe some status, and config pins..