Both layouts are wrong. You wired the zeners parallel, not in series. It's supposed to be like this:
*-----|<|-----|>|------*
1 ZD1 ZD2 2
That limits the voltage difference between the two pins to zener voltage + diode drop, i.e. 7,4V+0.7V = 8.1V.
If the voltage difference rises above that (1=10V, 2=0V for example), the reverse biased zener (ZD1) will break down and the other one (ZD2) will conduct anyway. So they just short out any voltage greater than 8.1V.
Thats a common technique used to protect parts of a circuit that must not go above a certain voltage, i.e. MOSFET gates.
A 3300µF output cap is very risky and defeats the purpose of your current limit. The current limit can limit (duh) the current that flows through your regulator, but it cannot limit the cap discharge current. That means, if you test a prototype and limit the current in case of a short, your circuit will blow up nontheless, because the output cap will discharge (read: tens or even hundreds of amps!) through your faulty circuit. AFTER that, the usual current limit kicks in. That short discharge is enough to kill most semiconductors and can even damage small tracks on your PCB.
In short: 3300µF is too much, better use ~100µF or less if possible.
Phil