Logic Analyzer Probe Impedance Matching Issue

[hjups]

Hi all,

For the past few weeks I have been working on designing a logic analyzer (for fun). My plan is to use ADCMP562s to do edge triggering, and then send the result off to an FPGA (a Dev board for now) to handle the data capturing.

I am stuck on the circuitry that precedes the ADCMP562s. I ended up buying an HP/Agilent/Keysight logic probe pod (16 probes on a 40 pin IDC), and a 40 pin twisted wire, controlled impedance cable. I figured that connecting the probes directly to the cable and ending with an impedance matched resistor would work (followed by ESD and current limiting protection). I was expecting to see an attenuated version of the input signal when I tested the setup with a 4 MHz square wave , but instead ended up with positive and negative spikes corresponding to the rising and falling edges of the test signal, respectively. I was able to reproduce this result in LTSPICE using the equivalent circuit that Keysight provides in their documentation.

I am at a loss as to what is going wrong / how to fix it. Or is this actually the intended result from the logic probe, to easily capture rising and falling edges? If so, what would be the best way to set up triggering with the ADCMP562?

It should be noted that the test signal comes out clean if I remove the controlled impedance cable and connect the oscilloscope directly to the output of the logic probe. I have also attached the equivalent SPICE circuit and simulation result (with the probe at the location: Ch2).

Thanks in advance.