To get back to the topic, I think you sometimes need 100MHz to measure some delays between clock/chip selects signals etc. For protocol decoding of 1MBaud, usually 10MHz are more than enough.
Anyway, I'd like to mention the Zeroplus "LogicCube" family.
I have both, an Open Logic Sniffer and a Zeroplus LAP-C(16032) which I patched to 128k (just ID in serial EEPROM).
Both are worth their money, but of course you have to live with some restrictions this way or the other.
The OLS is really neat for the price and I use it at work indeed sometimes when I need to analyze SPI buses. It's very portable as you don't have to install drivers and software. Then again, it has somewhat limited memory, the run length encoding leaves a bit to be desired, the GUI is neat to use, but still very basic and partly buggy: E.g. it still doesn't support bus grouping, the advanced (demon core) trigger options are still not accessible, the times displayed in 200MHz mode are still wrong, the pre-trigger time setup is more or less completely ignored. Also the lack of a case, the missing pull devices and input protection are a bit problematic for industrial use. Last but not least there are only a few protocol decoder available (the most important ones are there though).
The LAP-C(16032) is much more sturdy and the software is pretty good, although some things could be improved. I can even display analog data from my Owon SDS in parallel (though this is currently limited to 1k sampling depth). The ability to patch the low end 32k version to the middle range 128k version and the availability of >30 free protocols are the most interesting points. The major drawbacks are the very limited trigger possibilities and the download/installation process. You need to download every protocol separately though some are already included in the normal installations. Download takes forever and each protocol wastes a lot of disk space due to very large Chinese PDFs.
Also the design of the protocol decoders is a bit clumsy. E.g. to decode SDI and SDO, you have to double the CS and CLK signals, then group CS/CLK/SDI and CS/CLK/SDO to separate buses and apply the protocol decoder to both buses separately as this is possible with other LAs.