Hi all,
I've a question about logic analyzers and sample frequencies.
For example:
I've a logic analyzer that have a sample rate of 200Mhz.
I've a 20 Mhz clock(50% duty cycle) to sample and I've measured 16Mhz clock and sometimes 20Mhz clock when I sample this signal.
In the case I've a 50Mhz(50% duty cycle) clock to sample and a 100Mhz(50% duty cycle) clock to sample, I've measured respectively a 10/11Mhz clock and 15/20Mhz clock. In which of this two case I loose data(can't sample a logic 1 state for example) and how I can determinate relationship between sample clock, signal clock to sample and clock I get?