Losing Dead time after trifilar. Good on driver side, no DT on other side....

[Andy-In_over_my_head]

Aloha,
I'm using a TL494 in push/pull. The 2 outputs are going into an inverting and non inverting FET driver; Then each output to the trifilars (1:1:1)  first continuous winding. The non inverting has a 100nf cap in series from the driver to that one end of transformer winding and the inverting output is connected directly to the other end of that winding.
The other 2 output sets on the trifler (I apologize if I don't know correct terminology) are connected to the scope; probe and ground of each channel connected to each end of each winding.
When I scope the 2 outputs of the Fet drivers (ground clips to driver ground), I have a dead time that adjusts perfectly and I'm stoked.
When I probe the other side sides of the trifilar, I have no dead time between the 2 outputs and then I'm not so stoked.
The outputs are beautiful mirrors of each other.... with no dead time. When I adjust the dead time Pot, their duty cycle just varies...
Would there be a reason I would lose my dead time through the transformer?
I was thinking it's just ignorant probing... but I'm frustrated now.
If my description is too terrible, I will throw together a schematic and attach it.
I assumed there would be at least one person that could answer this with what I wrote..
Mahalo in advance.
(I did try and search this- Most likely my searches aren't going well since I don't know how to address the search correctly)

[T3sl4co1l]

Circuit?  Layout?

Mind that you may see dead time disappear at high duty%, because it all kind of mashes together.  Example (from a TL598 and transformer):



The GDT + load is a lowpass filter, L = leakage inductance, R = ESR, C = Cg(eff), which rolls off the corners of the waveform, and hopefully nothing more than that.  Trifilar helps a lot (it makes the leakage quite predictable), but it doesn't minimize it -- this is okay for smaller applications, but you may find you need a much lower impedance, to drive heavy gates fast enough (or to reduce switching time to raise efficiency), in which case you need to use multiple trifilar windings in parallel.

(What you're ultimately doing: this type of construction is called a transmission line transformer.  The impedance of the transmission line used, corresponds to the impedance where the transformer has its maximum bandwidth -- that is, its high frequency limit, corresponding to the electrical length of the winding.  If the wire length is about a meter, expect on the order of 50MHz cutoff, at the characteristic impedance of the line.  The impedance of trifilar is probably around 100 ohms.  If used at different impedances -- gate drives are usually quite a bit lower, maybe 50-10 ohms -- then the high frequency limit is that many times lower, and that's where the filtering comes from.  You can get the bandwidth back by wiring transmission lines in parallel.  Which does necessarily increase the isolation capacitance in the transformer, which is actually good in one (limited) sense, but, generally worse overall.  Note that, whatever way you build the transmission lines, they all need the same number of turns around a core, which can be a common core, so you get the same magnetizing inductance (and LF cutoff) as you have now.)

Tim

[Andy-In_over_my_head]

Here is a quick little attachment of a few more specific. (I don't see my attachment on preview so hopefully it shows up)
If still needed, I will clip in images from my scope. (I'm at work so photos from bench will have to wait until daughter is sleeping tonight)
I bought branded Gate drive transformers and tried all 3 types with this setup and got the same results.
I'm varying frequency from 50-225 kHz and I have a respectable dead time range...
I've added some specific part numbers just incase my mistakes are inexperience with the components I'm using.
Mahalo.

[Andy-In_over_my_head]

More details would be useful like frequency and how the driver transformer is constructed.
My project usually run at 40Khz into a ferrite toroidal driver transformer with 10uF coupling capacitor.

I added an attachment to a reply I just posted.
I tried to give enough information... If I need more, please let me know.
Mahalo

[Andy-In_over_my_head]

Circuit?  Layout?

I replied with an attachment. Hopefully I did well enough throwing it together in 5 minutes while distracted at work.
I've shown the datasheet for the transformers I am using as well as some part numbers and frequency I'm using.
I'm hoping this is just a simple issue. Though I can parallel the "GTD 100 100" or "GDT 050 100" since I have 2 of each of those.
I didn't think adding the mosfets would change this outcome... though I know a lot will change based on the mosfets I choose.
My inexperience whips my back end consistently though so I'm prepared to be wrong again..
Thankfully I invest obsessively into my home lab so I have all the equipment to test and large stocks of many types of components to fry.
Just don't have the knowledge to use all of my impulse ordered components... YET

Mahalo for the detailed response. Much appreciated.

[MagicSmoker]

...
When I scope the 2 outputs of the Fet drivers (ground clips to driver ground), I have a dead time that adjusts perfectly and I'm stoked.
When I probe the other side sides of the trifilar, I have no dead time between the 2 outputs and then I'm not so stoked.
The outputs are beautiful mirrors of each other.... with no dead time. When I adjust the dead time Pot, their duty cycle just varies...
Would there be a reason I would lose my dead time through the transformer?
...

This is quite common with gate driver transformers and is the result of the leakage inductance; it generally does not cause any problems in the actual circuit, but if you want to make sure do these 2 tests:

1. Look at the waveform across both secondaries with just a shunt 50 - 100 Ohm resistor present across each winding (no MOSFETs or other components).
2. Look at the current waveform going to the MOSFET drain(s) to see if there are short spikes at every transition from one leg to the other (ie - during when there should be deadtime).

The first test puts a real load on the transformer which (should) totally swamp the energy stored in the magnetizing and leakage inductances; you will almost certain want some shunt resistance across each secondary of the GDT in the actual circuit for the same reason.

The second test shows cross-conduction current. Note that some cross conduction current is okay - perhaps even desirable, as it suppresses ringing between the MOSFET Coss and main transformer leakage inductance - but once it exceeds about 1% of the full load current you can start having problems.


EDIT: grammar

[Andy-In_over_my_head]

Both outputs from the TL494 needed to be buffered with the same phase. Like both non-inverting.

They were both Non-inverted. I don't see how they could not be with pull up resistors on the 2 TL494 outputs. (I know I didn't show that, but I didn't think it was relevant.)

[Andy-In_over_my_head]

BTW,
Early TL494's had a problem that would cause the steering flip-flop to toggle multiple times if too much noise became present on pin 3.
This can be bad news for MOSFETs and IGBTs.
Other ICs at the time had double pulse suppression to prevent this problem.
The TI data PDF says   "Internal Circuitry Prohibits Double Pulse at Either Output", Yet I can't see anything relevant in the block diagram.

Ihttp://www.ti.com/lit/gpn/tl494

That's funny you say this. I've bought the TI brand, Sony brand and a Cheap Aliexpress brand to see if the different brands and manufacture times made a noticeable difference. Just haven't done testing yet.
(I have a sign in my lab that says "It's almost done though")
There's a lot of half finished projects during the learning curve. I just set things aside until I've learned enough to revisit the issues.

[Andy-In_over_my_head]

This is quite common with gate driver transformers and is the result of the leakage inductance; it generally does not cause any problems in the actual circuit, but if you want to make sure do these 2 tests:

1. Look at the waveform across both secondaries with just a shunt 50 - 100 Ohm resistor present across each winding (no MOSFETs or other components).
2. Look at the current waveform going to the MOSFET drain(s) to see if there are short spikes at every transition from one leg to the other (ie - during when there should be deadtime).

Mucho Mahalo.
I'll definitely give these a go.
I did check for spikes where deadtime would normally be. I was hoping for just that.
It just looks like it's filtering the deadtime completely though. I did have spikes on the rise and fall of the square waves but they were minimal.
I'll post some clippings from my scope of the responses of these tests.
Aloha.

[Andy-In_over_my_head]

The diagram shows one TC4429 inverting buffer and one TC4420 non-inverting buffer being used. So they are both really TC4420?

Oh... Negative. You are correct on the drivers. I assumed you meant the outputs of the 494.
I think the term "buffers" threw me off.
So I was under the impression the inverting/non-inverting pair was to create a push/pull on the transformer.
I would be stoked if replacing the 4429 with another 4420 corrected this.
I have a lot of "buffers" I've purchased for experimenting with. This one seemed fool proof since it only had an input and output while others have enable input pins as well.
I will swap the inverting one out for a non inverting and see what happens.
Mahalo for your time. It's greatly appreciated.