I need to understand and comprehend that circuit before I would feel comfortable using it. So ummm, R1 and R2 set a mid point reference (4.5V,) which goes to to the NII of IC1a. Initially the II will be low, so it will output high. I assume R4 is just a default pull-up, as it doesn't seem to have any use other than that.
Don't be shy about looking up parts and trawling datasheets if you have missing information, either -- as it happens, LM393 is a dual comparator with open collector outputs (and ~200ns response time). So, it simply won't do anything at all without R4. (A push-pull output type, like the LT1720, won't care about R4 at all, and it would indeed have no use!)
So Q1 will turn on allowing a kind of constant current charge of C1 through R5 with what's left of the emitter current before R6.
Not quite. Q1 is an emitter follower. One way to think of it: if the base is supplied with a resistor, the R+BJT can be transformed into an equivalent Req = R / hFE. This is handy for making stiff pull-ups (4.7k is pretty weak, but at hFE > 100, under 47 ohms looks like a good driver!), without wasting the current of such a low-value pullup (the comparator still only sees 4.7k).
The emitter follower is not saturated, so it doesn't suffer from storage time. (It's actually much faster than the LM393, which limits this circuit to 1-3MHz of questionably-useful range.)
Storage time is a phenomenon where, if you dump excessive current into the base to saturate the transistor, it takes a looooong time to come out of saturation. In fact, the B-E junction behaves like a battery with just the teeniest bit of charge stored in it: you can actually connect a resistor across B-E, and current will flow out of the base, through the resistor, until this charge runs out. While discharging, the voltage hovers around Vbe. If you don't use a pull-down resistor (your circuit showed a diode pumping up a capacitor, no pull-down, which is what triggered my remark), the voltage will sit there for a very long time (10s of microseconds), as it self-discharges. So, limited charge capacity, sort-of-constant-voltage during charge/discharge, and self-discharge: it looks like a very fast, very teeny battery!
t_stg is commonly listed on datasheets, with the switching parameters. Typical for a 2N3904 I believe is 200-250ns, which is an eternity compared to your LT1720 (~5ns response!), or even compared to the other parameters (rise/fall time ~30ns) of the same transistor.
The reason for that is, the "saturated switch" test is conducted at hFE = 10, meaning, hFE might be 100 or more (for linear operation), and you always need a little more to make it saturate nicely. By going all the way down to hFE = 10, you get a nice low Vce(sat), but you also store a lot of base charge.
Moral: if you want BJTs to switch fast, you need to pull current out of the base as well. Like MOSFETs, but in that case you have explicit gate capacitance. Well, the base does too, and then some. It's NOT a current controlled device, you need to yank that base voltage around to get it to do what you want!
R3 sets up the trigger hysteresis, making the charge threshold higher than 4.5V, when the cap reaches this charge threshold the comparator latches to low output turning Q1 off, the hysteresis from R3 then sets the discharge threshold of the cap below 4.5V,. The cap discharges through R5 and R6 until it reaches the discharge threshold and the comparator latches high again, and the process repeats. Hopefully I've understood that now.
Yup!
You can even calculate the threshold shift:
The Thevenin equivalent of R1 || R2 is 5k and 4.5V. R3 has about 8V of swing on the 'hot' end (the emitter follower doesn't quite pull all the way up to +9V, or down to 0V), and acts as a 22k + 5k voltage divider, so that the NII swing is 8V * 5k / (22k + 5k) = 1.48V. This is nearly symmetrical around the 4.5V mean, so the actual thresholds will be half above and half below, or about 3.75 and 5.25V.
The threshold voltages are, of course, the P-P swing of the capacitor voltage, and also the useful range of the "CV In" connection. Which sucks a little, because if you hook up an error amp to CV In, its output will swing 0-9V (if it's a R2R type op-amp), which means the first 0-3.75V and the last 5.25-9V are useless dead zone. You can reduce the range with a resistor divider (much like R3 into R1 and R2 does here) to fix that.
I already understand the PWM comparator part 
I notice you've put a little hysteresis on the PWM generator as well, I didn't do that because of this problem I have with always thinking ideally. I'll have to get out of that habit.
The purpose here is to give just a little bit of "snappiness", so the output (hopefully) doesn't make half-assed pulses around the edges (when CV In ~= top or bottom peak voltage). If the edges of the ramp wave are perfectly sharp (they aren't -- the LM393 takes maybe 50-100ns to swing, but even if it were instantaneous), the output PWM should ideally go to perfectly fine slivers of pulses, for CV very near the peak. But real comparators are sloppy, and real circuits are noisy. You can actually play with the "fine slivers" condition, but it's more practical to simply cut them off entirely.
The effect of hysteresis is, it won't switch for an input swing less than threshold. So, for inputs hovering right over the peak voltage, just under threshold will produce no pulses at all, and just over, it will only make a certain minimum width pulse or larger. Very thin pulses are limited by response time and rise time, and end up sloppy. If you're following it up with switching transistors, you don't want them turning halfway-on before going right off again, because failed switching means way more power dissipation than good clean switching.
EDIT: Will that be ok at a period of 4us? I've modeled the circuit in LTSpice (using an LT1720 which has super fast response time) and 5V supply, changed C1 to 220p and R5 to 12k and that gives just under a 4us period. But I'm worried about it being in this spooky physics region with storage times.
Yeah, it's fine there. You don't need the transistor at all, for LT1720; in that case, it's probably happy anywhere from 250kHz to 100MHz.
Also do you think I should think about using something a little better than a 7805 for the 5V rail? The loads and switching speed being used would cause it immense grief I would think.
As long as you have enough bypass capacitance, the high frequencies won't even touch it. Its internal loop response (it's an error amplifier, guess what!
) rolls off in the 100s of kHz, so it just looks like an impedance at those kinds of frequencies. (The 7805 uses an emitter follower, so it actually behaves very well at high frequency, tending towards a moderate resistance, which tends to help dampen supply resonances. LDOs are common-emitter or common-source devices and generally have far higher impedances, often reactive at that (inductive, or worse) -- this is why LDOs generally need capacitors with known ESR, and if the datasheet isn't talking about capacitors, ESR and stability, run away and find a better one!)
Tim
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