LTspice Beginner Question: Why simulation result is wrong?

[gdx001]

Hello everyone,

I am new to LTspice, and I am trying to simulate a "latching" circuit, which is the Fig 3 on http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/electronic-circuits/push-button-switch-turn-on/latching-toggle-power-switch. I put the schematic in attachment.

I can understand how this circuit works, and I actually made it work on my breadboard already. However my LTSpice simulation gives me totally different result, which I think is incorrect. I attached my asc file and the simulation result.

The first thing I don't understand in the simulation result, is the voltage on point A, who goes to zero at the beginning. It should be very close to 5V instead (when there is current to charge C2, point A should be 5*10/11~=4.5V). Because of the wrong voltage on point A, the P-MOSFET conducts and I get output voltage at the beginning, which also pulls up the C point. The circuit is latched without pressing the button, which is not expected.

This simulation result doesn't seem to make sense. When testing this circuit on breadboard, there was no output voltage until I tap the button.

Did I miss something? Can someone give me idea how this is happening? Thanks in advance.

[Jay_Diddy_B]

Hi,

You need to change the simulation command from:

.tran 10

to

.tran 10 startup


This can be done by checking the box 'Start External DC supply voltages at 0V'

This will cause the circuit to start with the supplies at zero volts.

Regards,

Jay_Diddy_B

[MagicSmoker]

In addition to the above comment, you also need to change the parameters of V1 so that the period is less than the simulation time - try 5, for a simulation time of 10, for example - so that you can see both the turn on and turn off behavior.

[Ian.M]

I doubt you really wanted the switch control signal to have a period of over half an hour!

Try PULSE(0 1 2 1u 1u 0.4 2) for source V1.  The 50ms transitions combined with the negative hysterisis for the switch model which forces a smooth resistance change rather than the step change you'd get from a clean mechanical contact were screwing up the results.  A very small negative hysterisis + small risetime/falltime on the drive waveform can be useful if the switch is being used as a chopper as otherwise the discontinuity at the moment of switching can significantly slow the simulation, but for general use to simulate a user control, you neither want nor need that.

1 Meg is a very low off-resistance for a mechanical switch.  Using .model MYSW sw(Ron=0.3 Roff=30Meg Vt=0.5) would be a better approximation to a real switch, though without any contact bounce it wont be realistic.

Whether or not you use the startup option for .tran makes little difference other than the initial state, on or off.  startup is probably more realistic.

[gdx001]

Thank you Jay_Diddy_B, this really helps 

Now I understand that LTspice needs this option to simulate the "power on" behavior properly. If possible, I would like to figure out how LTspice calculates the voltage on point A, when 'Start External DC supply voltages at 0V' option is not turned on. Even if LTspice assumes the capacitor C2 is fully charged at the beginning, point A should be 5V instead. The only possibility that point A goes 0V, is that M1 conducts and short A to ground. But if point A is not low enough, M2 will not conduct and point C will not be pulled up, as a result M1 will not conduct...  This seems to be "which came first: the chicken or the egg?" question.

I would like to understand how LTspice works without the 'Start External DC supply voltages at 0V' option, so I will know in which scenario should I turn this option on/off. Thank you for the help.

You need to change the simulation command from:

.tran 10

to

.tran 10 startup

[gdx001]

Thank you MagicSmoker and Ian.M, you gave me very good suggestions too, appreciate it

[Ian.M]

Now I understand that LTspice needs this option to simulate the "power on" behavior properly. If possible, I would like to figure out how LTspice calculates the voltage on point A, when 'Start External DC supply voltages at 0V' option is not turned on. Even if LTspice assumes the capacitor C2 is fully charged at the beginning, point A should be 5V instead. The only possibility that point A goes 0V, is that M1 conducts and short A to ground. But if point A is not low enough, M2 will not conduct and point C will not be pulled up, as a result M1 will not conduct...  This seems to be "which came first: the chicken or the egg?" question.

I would like to understand how LTspice works without the 'Start External DC supply voltages at 0V' option, so I will know in which scenario should I turn this option on/off.

See the .op simulation command in the LTspice help file.   Unless you tell it not to (by adding the uic switch to .tran), it performs an .op analysis to attempt to establish steady state DC conditions for the circuit.   For the .op analysis it treats inductors as open circuits and capacitors as short circuits, unless they have been given initial voltages/currents by the .ic command.  It tries several iterative methods to find a steady state solution, but it is possible for it to fail to find one which will prevent further simulation.  Using the startup switch vastly increases the probability that it will be able to find an initial steady state solution.   You'll also want to look up .tran and .ic in the help file.

[gdx001]

Thanks Ian.M,

I read the .op command in the help file, and understand it treats inductors as short circuits and capacitors as open circuits (not the other way around ). But still I can not figure out how it can calculate the voltage on A to 0V. If consider C2 as short circuits, point A should be 4.5V; if take C2 as open circuits, point A should be 5V instead.

Anyway, it seems not that easy to figure it out, at least to beginners like me. Will it be safe to always turn on the "startup" switch? If the answer is positive I will just stick to it 

[Ian.M]

Sorry about the confusion - at the moment of switchon capacitors appear as shorts and inductors as opens as there hasn't been any time for them to charge or flux to build up respectively, but for the .op STEADY STATE analysis, the simulation is trying to find what would be the solution after infinite time which is completely the opposite.  I had a brain fart and posted the zero time equivalents instead of the steady state ones. 

As LTspice is proprietary we don't really know *how* it iterates to find the operating point, apart from whatever description LT have given us, but several of the phases appear to be similar to Berkley SPICE 3's .op  analysis.  As Berkley SPICE is open source and was the first SPICE program, it can shed some light on the behaviour of its descendants and compatibles.  See SPICE algorithms and internals - Imperial College London

The .tran startup switch is a hack - it ramps the DC sources linearly in the first 20us to crudely approximate the switch-on behaviour of a real circuit with limited current supplies charging decoupled supply rails.   However it makes the .op analysis useless for determining the actual DC operating point of the circuit as it then does the analysis with all DC sources at 0V or 0A.

LTspice can label nodes with their voltage (right click:View:Place .op data label),  or you can right click a .op data label and change it from $ to an expression so it no longer needs to be attached to a node.  Unfortunately all .op data label values are taken from the .op analysis, and there is no way to display .measure results directly on the schematic.  That means if you disable the .op analysis with the .tran uic flag they display as or if you smash it with  the .tran startup flag, they display as 0V (or 0A etc.).  N.B. You cant place a new .op data label unless you've just run an analysis that include .op. (i.e. .tran without uic or an explicit .op)

The order of preference is therefore:

• Plain .tran with no flags
• .tran startup
• .tran uic

[li].tran startup uic
[/li][/list]
Reasons for moving down this list may include undesirable transient behaviour at startup, excessive .op anaysis time, or failure of .op analysis causing .tran simulation failure.  The uic flag forces .tran to start with all nodes at 0V (i.e. all capacitors discharged) and all inductors at zero current except where explicitly over-ridden by a .ic command.  This can result in pathological behaviour unless your circuit has realistic parasitic resistances. 

However the combo startup uic is particularly useful for analysing power supplies quickly, where you don't really care what happens in the first cycle, but do care what happens when the output cap reaches a certain voltage, so you can skip simulating 99% of the earlier cycles by setting appropriate .ic conditions for nodes to precharge caps to a little under the target voltage so it only has to simulate enough cycles to settle into normal operation then a few more to reach the point you want to take measurements at.