LTspice frustration ...

[LEECH666]

Hello, once again I need help.

I am trying to simulate a little circuit that I recently build up. It's a little virtual ground circuit that splits a DC voltage into a negative and positive voltage.

In my example I want to split 12V into ±6V, but for some reason it doesn't work and splits the supply into something totally unexpected (see pictures).

I could swear that I wired up the same circuit on my pc at work during lunch break a few days ago and that it worked the way it should work (±6V, and not +10,5V and -1.4V).

What am I doing wrong here? How can I trust LTspice at all if even relatively trivial circuits like this one already fail to simulate correctly? Have I fallen in "a trap for young players"?

I feel like I've come about errors like this quite some times now, and I never know how to fix them. It's not inducing a lot of confidence for me in LTspice, that's for sure.

No idea what's wrong here really. Bad combination of selected component models? Corrupted LTspice installation?

What's the right approach to avoid stuff like this. I know the circuit works, since I wired it up IRL already, but I want to be able to simulate circuits like that too, that's why I am asking.

I find this really frustrating ...

Any advise?

Florian

[Harvs]

Looks to me like you've got the inputs of the op-amp the wrong way around.  The feedback should be going to the inverting input (-).

Edit: attached is a sim of the same circuit with the op-amp flipped, works fine for me.

[LEECH666]

That's probably it. *facepalm*

Apparently I redrew the circuit incorrectly in my cad system and I used that drawing as a reference for my second LTspice simulation. I used the original schematic at work.

Let me take a look ...

[LEECH666]

This is weird ... looks like the original schematic is wrong too?



I am pretty sure I also wired it up that way in my little perfboard circuit.

Gonna check that ...

[Harvs]

Nope, just the op-amp is drawn differently.  Look at the actual symbols on the op-amp, not just the position of them.

Cheers

[BravoV]

Get some sleep, really believe after you wake up, everything will be better and trust me, you will spot your mistake. 






Hint .... look at the (+) and (-) sign, NOT the orientation of the op-amp input

[Hex173t]

This is a neat circuit.  For the sake of learning, what is the purpose of C4?  I removed it and there seems to be no 'simulated' difference in static output.

[LEECH666]

Okay I see my fault now, but it's tricky. As I mentioned before I redrew the circuit in my CAD program, because I'll probably use this circuit on my dummy load PCB. Anyway for whatever reason I used a wrong OP symbol (with + and - switched, - = pin 3, + = pin 2) in my CAD library. That and me not being thorough enough. I blame it on the slight headache I've got  . Anyway thanks for the help and making me find that error in my lib. Btw, that's probably the reason why I wired it up correctly too, since I just went by pin numbers without paying too much attention to + and -.

This is a neat circuit.  For the sake of learning, what is the purpose of C4?  I removed it and there seems to be no 'simulated' difference in static output.

I didn't come up with this circuit. This seems to be the source: http://www.redcircuits.com/Page114.htm
The circuit is meant to be an extension to this one: http://www.redcircuits.com/Page36.htm
Maybe the cap is related to that ... it's probably redundant (?) but I've got it on my perfboard too.

[IvoS]

I think C4 + R1 is a low pass filter.

[LEECH666]

Picture of the working circuit ...



Sorry, had to take it with my phone as I loaned my digicam to my flat mate.

Thanks again for the help,
Florian

[peter.mitchell]

just wondering how much current that can provide without the rails playing up (dipping/going out of balance)?

[Shuggsy]

Very cool Florian! I'm interested to see this working in your dummy load project. Your LTSpice/CAD library troubles remind me of Bob Pease and his... "appreciation" for simulations

This is a neat circuit.  For the sake of learning, what is the purpose of C4?  I removed it and there seems to be no 'simulated' difference in static output.

C4 is likely there to help with high-frequency, low power transients on the positive rail. C5 serves the same purpose on the negative rail. The larger caps (C2, C3) provide overall bypassing for the rails. The 100nF caps handle the higher-frequency fluctuation events better than the larger caps (and vice-versa... larger caps handle the big fluctuation events better than the smaller caps). What's really happening is that you want to create as low an impedance path to the power rails as possible. If you have some chip way out from the power rail, it has the resistance and inductance of the entire path to the chip to deal with whenever the chip needs a little power like a switching event in some internal transistor. To help alleviate this, you put a bypass capacitor near the component to provide a little local power storage that, for that transient event, provide a very low impedance path to the power rail. As the capacitor drains, its impedance to the nominal voltage will increase (as the voltage on it will drop as it delivers the charge/power to the device).

So, larger caps have a low impedance at lower frequencies while smaller caps (smaller both in capacitance and physical size) have a low impedance for higher frequencies. See this app note from Intersil for a quick rundown of bypassing in general as well as why you might use smaller or larger caps in some situations, what the differences are, and some general guidelines: http://www.intersil.com/content/dam/Intersil/documents/an13/an1325.pdf

[LEECH666]

But unlike Bob Pease I am just an idiot and not an analog guru.

I will try to do some (limited) current tests of the circuit later today.

I suspect that the BC328/BC338 that the transistors I used instead of the the higher power BD437/BD438 are a bit wimpy in comparison but he TS271C OPs that I am going to use for my dumm load are fairly low power ones (Icc < 2mA) so I assume that they will be sufficient.

I am at work atm, and I just checked my original simulation file, and yes I drew it correctly the first time. The problem was really in my cad library, while the I connected it to the right pin numbers in my CAD tool I only looked at the + / - designator on the smybol  to redraw it in LTspice.

Cheers,
Florian

//EDIT: Misspelled idiot ... go figure ..

[LEECH666]

Okay tested the circuit for a little but then I blew it up. It kinda worked as expected with two pots on the outputs to GND. I was able to draw ~100mA from both rails, however the positive rail was much more stable.

At 100mA the positive rail was still at 6V while the negative rail sunk from -6 to -5V.

Guess I've pushed it one too many times beyond its limits. I assume either the OP is blown or one of the transistors as the voltages now read -10V and 2V.

Well I will call it quits for today ...

Cheers,
Florian