LTSpice - Linear regulator - constant current mode - loop gain analysis

[not1xor1]

Hi,
I wonder what is the correct method to simulate the loop gain/phase margin of linear regulators working in constant current mode.

I couldn't find anything with google (may be I used the wrong terms), so I devised this test circuit where I unconnected the voltage regulation part and connected the output to ground. That produced something which looks like a correct bodeplot:



BTW I found some TI document about using huge inductor and capacitor in loop gain spice simulations and so I used 1 TeraHenry/1 TeraFarad (1 microOhm parasitic resistance) components to provide separate paths to DC and AC sources.

Anyway I'm unsure the result I got is correct (i.e. is meaningful regarding real circuits)  .
I'd like to get some feedback.

Thanks

[Kleinstein]

The loop gain analysis looks OK. There is even no need for the capacitor and inductor - it should work the same ways without.

However keep in mind that this is the short circuit case.

[not1xor1]

The loop gain analysis looks OK. There is even no need for the capacitor and inductor - it should work the same ways without.

However keep in mind that this is the short circuit case.

I used the large inductor/capacitor trick because I had got strange results in other tests with the 0VDC/1VAC source.
That was probably caused by some other stupid mistake of mine (may be a non 0? series resistance).

At first I could not succeed in getting any significative results with a non short-circuit load, but then I realized I had to plot the rate of the voltage at the Rsense terminals, i.e. V(output,load)/V(fb,load) in the schematic below


Thanks for your valuable support