LTSPICE linear regulator loop gain stability analysis

[not1xor1]

Hi
I just can't understand how to make a loop gain stability analysis of a linear power supply when the control circuit supply is referenced to the positive output.

Here is a simplified schematic


thanks

[Kleinstein]

The test AC source goes somewhere in the loop, where signal flow is from voltage and one direction only. So the obvious place is in series to the non inverting input of the OP.

One should get the same result for the loop gain with the source at a different point in the loop, like at the output of the OP.

[not1xor1]

Hi Kleinstein

thanks for your reply

I had a look at the "LTspice Stability of Op Amp Circuits" movie and succeeded in running the simulation in a different kind of circuit:



I already tried to put the AC source where you suggested (and in various other position along the signal path), but I can't understand how to interpret the result as I never got a gain greater than 0dB (I also tried various other ratios):



I'm not even sure it is my fault as I saw various times LTSpice behave in odd ways with my setup (kubuntu 14.04 + wine)

For instance the LT4320 example did not work correctly with LTSpice IV, but few days ago I installed the latest version (XVII) and now it works as expected

any suggestion?

thanks

[Kleinstein]

In this circuit it matters, where you put the reference point: if the voltage is measured relative to the GND point, than there is a second parallel path to the inverting input. And thus analysis does not work as expected. It would work if the output is used as reference point (so use difference probe with pulling the pointer).
So it should work better with the source at the output of the OP or the source of the FET.


With an possibly unstable circuit one might also have to check the operating point - sometimes it would calculate for a wrong DC point.

[LvW]

Hi
I just can't understand how to make a loop gain stability analysis of a linear power supply when the control circuit supply is referenced to the positive output.
Here is a simplified schematic

not1xor1, I must admit that - up to now - I have never seen an LDO circuit like yours. Are you sure that it works?.
Normally, there is a GROUNDED and FIXED reference voltage at the non-inv. opamp input and the inverting input is connected to the resistive voltage divider. In your case, the reference is not fixed but connected to the voltage to be controlled!.

[Kleinstein]

The circuit is not that unusual: it just lacks the usual capacitor in feedback at the OP and the resistor at the inverting input that goes with it. If the OP is rather slow and well behaved, it might work without it.

[Cerebus]

Hi
I just can't understand how to make a loop gain stability analysis of a linear power supply when the control circuit supply is referenced to the positive output.
Here is a simplified schematic

not1xor1, I must admit that - up to now - I have never seen an LDO circuit like yours. Are you sure that it works?.
Normally, there is a GROUNDED and FIXED reference voltage at the non-inv. opamp input and the inverting input is connected to the resistive voltage divider. In your case, the reference is not fixed but connected to the voltage to be controlled!.

Mentally turn it upside down and ignore the instinct that you have that 'ground' is fixed and you'll see that all is fine. It's a fairly classic topology, used in many bench PSUs by HP and others. Note that everything, including power for the op amp is referenced to the FET output and that it's balancing current through the negative rail sense resistor (R16) against current from the reference via R17.

[Jay_Diddy_B]

Hi group,

In this circuit the output node is really the small signal ground and LTspice ground is the output. The loop gain can be modeled like this:



Plot the following expression: V(output)/V(output,b) and you will get this, which is the loop gain:



I have attached the LTspice model.

Regards,

Jay_Diddy_B

[ZeTeX]

Hi group,

In this circuit the output node is really the small signal ground and LTspice ground is the output. The loop gain can be modeled like this:



Plot the following expression: V(output)/V(output,b) and you will get this, which is the loop gain:



I have attached the LTspice model.

Regards,

Jay_Diddy_B

Hi,
Can you please tell me if I'm doing it right?

thanks

[Jay_Diddy_B]

Hi,
Can you please tell me if I'm doing it right?

thanks

In your circuit the loop gain is displayed by plotting:

V(out)/V(b)


A shown, you probably have too much bandwidth.

Regards,

Jay_Diddy_B

[LvW]

Hi group,

In this circuit the output node is really the small signal ground and LTspice ground is the output. The loop gain can be modeled like this:

I have attached the LTspice model.

Regards,

Jay_Diddy_B

Jay_Diddy_B: Sorry to say - but your loop gain model is wrong.
Loop gain is the gain of an open feedback loop. But it is easy to see that in your model the loop remains closed.
(For clarification: I do not speak about the last circuit from zeteX. Here, the simulation profile is correct).

[not1xor1]

Hi everybody and thanks for your contributes 

LvW:
As stated by others this is a quite common PSU circuit topology.

Kleinstein:
This is just an over simplified test circuit whose only purpose was to understand how to perform the loop gain simulation.

Jay_Diddy_B:
This is a common but odd circuit topology. The control circuit bootstrapped supply and reference make it a difficult to understand.

I had already tried to put the AC source as you suggested, considering the GND as the output, but had failed to work out the correct V ratio.

Surely there is no need to specify I'm just an amateur and have not yet fully grasped the meaning of the subject 

In any case how should I interpret the result? It is just 40° of phase margin while it should be at least 45° to grant a stable behaviour under any kind of load... shouldn't it?

thanks

[not1xor1]

Hi,
Can you please tell me if I'm doing it right?

thanks
[/quote]

you should modify the AC simulation to display up to at least 10MHz: .ac dec 100 1 10MEG
so you can cross the cursor with the 0dB gain point and see that in your case you have just 11-12° of phase margin, i.e. your circuit might be unstable (if I've not misunderstood the topic  )

[not1xor1]

Hi group,

In this circuit the output node is really the small signal ground and LTspice ground is the output. The loop gain can be modeled like this:

I have attached the LTspice model.

Regards,

Jay_Diddy_B

Jay_Diddy_B: Sorry to say - but your loop gain model is wrong.
Loop gain is the gain of an open feedback loop. But it is easy to see that in your model the loop remains closed.
(For clarification: I do not speak about the last circuit from zeteX. Here, the simulation profile is correct).

The closed loop gain of the circuit is just about 15.6dB, while in Jay's plot you can see gain exceeding 100dB (more than 140dB if you plot from 1 milliHertz) so I think he's right.

BTW you get the same plot if you place the AC source before the non inverting input (as suggested by Kleinstein) and plot V(fb,output)/V(inp,output) (as suggested by Jay)

[ZeTeX]

Hi,
Can you please tell me if I'm doing it right?

thanks

you should modify the AC simulation to display up to at least 10MHz: .ac dec 100 1 10MEG
so you can cross the cursor with the 0dB gain point and see that in your case you have just 11-12° of phase margin, i.e. your circuit might be unstable (if I've not misunderstood the topic  )
[/quote]
Yes, I fixed it by doing this:

[Kleinstein]

Form just looking at the loop gain, it is not easy possible to say how the circuit will behave with a different load. Having a 45 phase margin does not guarantee stability with any load. This is more like no ringing with that particular load. The loop gain and thus the phase margin depends on the load impedance. With a poor design even an 80 degree phase margin can turn negative with the wrong load.

To judge stability with different loads, it is much easier to look at the output impedance curve. If the output impedance has less than 90 degree phase shift, it will be stable with any passive (that is less than 90 deg. phase shift itself) load. It can still show a lot of ringing if the sum of phase shifts of regulator and load is close to 180 degree.

[ZeTeX]

look at the output impedance curve. If the output impedance has less than 90 degree phase shift, it will be stable with any passive (that is less than 90 deg. phase shift itself) load. It can still show a lot of ringing if the sum of phase shifts of regulator and load is close to 180 degree.

OK, so how do you plot the output impedance curve and check the phase shift for example in my circuit?

[Kleinstein]

Plotting the output impedance works with a AC current source (spice element) at the output, and plotting the output voltage. With an AC amplitude of 1 (A), output is directly in Ohms or dB relative to 1 Ohm.

[ZeTeX]

Plotting the output impedance works with a AC current source (spice element) at the output, and plotting the output voltage. With an AC amplitude of 1 (A), output is directly in Ohms or dB relative to 1 Ohm.

I'm getting -90 phase margin at 0db, am I doing this right? as you can see I've placed a current source with an AC amplitude of 1 in the output and I'm plotting the output.
https://i.gyazo.com/add283d1210ca466bfdb2b606539e3e1.png

[Kleinstein]

One does not get the classical phase margins from the output impedance curve. The 0 dB point ist just 1 Ohms and has no special meaning. The interesting point is one how close the curve comes to 90 degree and 270 degree at any frequency. The other important point is the maximum impedance so in this case about 35 dB_Ohm or something like 50 Ohms (maybe a little more as the actual peak might be missed)
 
The example curve shows a phase shift of very close to 90 degrees in the 10 Hz - 10 kHz range: so it behaves very much like an low loss inductor. At 5 kHz 1 Ohms impedance is reached, thus the effective inductance is about 30 µH.Together with the rather low ESR output capacitor this gives the resonance at about 15 kHz. It looks like still marginally stable, but there will be a excessive ringing, due to the high Q resonance visible.

Right of the resonance the output capacitor is setting the output impedance.

[ZeTeX]

One does not get the classical phase margins from the output impedance curve. The 0 dB point ist just 1 Ohms and has no special meaning. The interesting point is one how close the curve comes to 90 degree and 270 degree at any frequency. The other important point is the maximum impedance so in this case about 35 dB_Ohm or something like 50 Ohms (maybe a little more as the actual peak might be missed)
 
The example curve shows a phase shift of very close to 90 degrees in the 10 Hz - 10 kHz range: so it behaves very much like an low loss inductor. At 5 kHz 1 Ohms impedance is reached, thus the effective inductance is about 30 µH.Together with the rather low ESR output capacitor this gives the resonance at about 15 kHz. It looks like still marginally stable, but there will be a excessive ringing, due to the high Q resonance visible.

Right of the resonance the output capacitor is setting the output impedance.

So to minimize the chances to oscillation, one should reduce the effective inductance?

[LvW]

The closed loop gain of the circuit is just about 15.6dB, while in Jay's plot you can see gain exceeding 100dB (more than 140dB if you plot from 1 milliHertz) so I think he's right.

The closed-loop gain you are speaking of is referred to the input voltage Vin - correct?
However, this is irrelevant since this source must be set to ZERO during loop gain measurements.

BTW you get the same plot if you place the AC source before the non inverting input (as suggested by Kleinstein) and plot V(fb,output)/V(inp,output) (as suggested by Jay)

No - thats impossible. The gain myight be in the same order (large) - however, the measurement (simulation) does not comply with the loop gain definition. The loop is still closed - however, the input to this closed loop now is at the opamp. Therefore, you must NOT compare it with the closed-looop gain related to Vin. The test source must be placed WITHIN the loop (thereby open it, according to Middlebrooks analyses).

[Kleinstein]

To get a voltage regulator that behaved well with capacitive load, one should avoid the regulator to behave like a near perfect inductor. The value of the simulated inductance is not that important - it sets the frequency where the circuit might ring, though a low equivalent inductance somewhat helps to get a fast transient response. The important part is to add some damping to the inductance. So the phase should not go close to -90 degree, but more like stay at -110 to -100.  A first improvement would be having more series resistance with the output capacitor.

The reason the circuit behaves that strange is likely that there is no DC current flowing and thus the transistors will not be active. So the response also depends on the DC current. So testing with different superimposed DC currents is still needed (this also applies to the loop gain way of looking at it).

[LvW]

The reason the circuit behaves that strange is likely that there is no DC current flowing and thus the transistors will not be active. So the response also depends on the DC current. So testing with different superimposed DC currents is still needed (this also applies to the loop gain way of looking at it).

Yes - I agree to this. It is important to realize that the circuit under discussion is not a "classical" control loop with follower characteristics (ouitput shall follow input changes). In contrary, the output must NOT react upon input changes - hence, we must handle it as a so-called "disturbance control" system.

[Jay_Diddy_B]

Hi group,

In this circuit the output node is really the small signal ground and LTspice ground is the output. The loop gain can be modeled like this:

I have attached the LTspice model.

Regards,

Jay_Diddy_B

Jay_Diddy_B: Sorry to say - but your loop gain model is wrong.
Loop gain is the gain of an open feedback loop. But it is easy to see that in your model the loop remains closed.
(For clarification: I do not speak about the last circuit from zeteX. Here, the simulation profile is correct).

I do not understand your concerns with my model. It an implementation of the method pioneered by Middlebrook.

Consider this circuit:



This is a more conventional LDO. I have placed the disturbance source V3 at the top of the divider (the classical position). The control loop is trying to stabilize the voltage at the node marked B. So if we have lots of loop gain the voltage at B will be constant and all the disturbance will appear on node A. When we are the loop crossover frequency the signals at A and B are equal in amplitude but phase shift.

I can plot the results:



The results show a dominant pole formed from (R2//R3 +R4) and C1. Which is the expected resulted.


If I return to the original posters circuit, but I move the disturbance to a difference position:



The disturbance source is clearly, within the control loop. The signals in this circuit are measured with respect to the output node, because the output node in this circuit is the small-signal ground.


I get this result:



Which is identical to the results shown in my earlier message.


Regards,

Jay_Diddy_B

[LvW]

I do not understand your concerns with my model. It an implementation of the method pioneered by Middlebrook.

My comment (as I have mentioned already) was related to the scheme as shown at the beginning of your reply#7  .
Here you did not follow the Middlebrook approach because the test source was outside the loop.

[MrAl]

Hello,

Just a quick note...

It is always good to try a step response also to see just how 'stable' the circuit really is and if the response to a step input is acceptable.  A little ringing may be acceptable or may not be depending on your application.

[not1xor1]

Zetek:
right click on the dB rule and in the Representation group select the Linear radiobutton to directly get the ? scale (see screenshots below)

Kleinstein:
if I set the DC component of the current source to 1 the impedance Q disappears (see screenshots).
But what should that mean? I've no hint

MrAl
the real circuit (not the simplified one) behaves correctly with 5mA-5A load, 10µs rize/fall .2s wide steps (at least in the simulator)
I also simulated various kinds of mosfet preregulators. But that will be matter for another future thread .

0A DC load impedance plot:



1A DC load impedance plot:

[Kleinstein]

More current increases the loop gain (of the MOSFET) and this way reduces the inductance. This way the ESR of the output capacitor can become more effective to dampen the resonance. A MOSFETs also get slower when operating at very low current.

This dependence on the current can be a problem for a supply, as the regulator should be stable at low output currents too. One common countermeasure is to add more minimum load, so the MOSFET will hopefully always see something like 10-100 mA of current. However this is not that simple: even if there is a constant current sink as a minimum load, it is possible that this current flows into an capacitive load or just the output capacitor if there is some ringing at lower frequency. Another point is adding a resistor at the source pin, usually also used for current limiting, this will limit the change for very high currents, as it limits the trans-conductance of the MOSFET - though is does not help at the low current end.

It is sometimes still done this way, despite of not being a good solution. A good solution would be making the output stage capable of 2 quadrant operation and this way ensure a minimum speed of response at all currents, even negative.

The circuit still has a problem in having an output impedance that looks very much like an ideal inductor and thus will show ringing / resonances with an highly capacitive load. If you add something like 1000µF with low ESR, the resonance should be back, even with 1 A of DC.

The logarithmic scale might be a little unusual for impedance, but has its advantages, as one can see the lower values too.

[Jay_Diddy_B]

I do not understand your concerns with my model. It an implementation of the method pioneered by Middlebrook.

My comment (as I have mentioned already) was related to the scheme as shown at the beginning of your reply#7  .
Here you did not follow the Middlebrook approach because the test source was outside the loop.

I still don't understand your concern. Consider these models:



The left model is a regulator with a negative output voltage. V17 is the reference. and V19 is the disturbance source, placed in the 'top' of the divider. Apart from having a negative output voltage this is a very conventional location for the disturbance source.

The control loop will try and hold the voltage at node e constant with respect to ground. In this circuit the gain from the reference to the output is Vout = Vref(1+ R21/R20)

The centre model has been modified to move the reference to the location used by the original poster. The operation is similar. The gain from the reference to the output is Vout = Vref(R14/R13), slightly different.

The third model the output connection and the ground have been swapped to make a positive output voltage. This is possible because all the supplies and references are floating.

If I measure the loop gain for all these models, providing I use the correct small-signal ground, I get identical results.




This validates the location chosen for the disturbance source.

Note: The op-amp has been replaced by a voltage controlled voltage source, E, with suitable gain and bandwidth. When I used a real op-amp I did not get the expected results. I believe that this is due to some limitation in the LTspice models.

It is obvious, by inspection, that the loop gain should not change by moving the ground, that is going from the centre model to the one on the left.

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

I am not fan of this circuit. These are the main elements in the control loop, as shown.

1) there is a pole that comes from the op-amp. This contributes 90 degrees of phase shift.

2) the transconductance of the MOSFET, results in a current source, which forms another low frequency pole with the output capacitor.

Combined we have a low frequency double pole. This can be seen on the loop gain plots as a slope of -40dB/decade.

There is also a zero formed by the ESR of the output capacitor. It is this zero from the ESR that is keeping the loop stable.

Regards,

Jay_Diddy_B

[LvW]

I still don't understand your concern. Consider these models:

Jay_Diddy_B, you don`t understand my concern?
For clarification, we do not need new or modified models.
You only must answer my question:
Is the ac test source in all three simulation schemes (post#7 and your last post) inside the feedback loop?
Obviously, the answer is NO!
Instead, these sources are grounded and the loop is still closed. This is the result of a simple visual inspection and cannot be denied.   
Hence, all of your simulation results might be identical - but neither shows the correct loop gain.

For illustration purposes, Let me discuss a simple example:
Consider the classical non-inverting opamp amplifier (feedback chain R2-R1, with R1 connected to ground.)
For testing the loop gain, we open  the feedback loop and place a test source BETWEEN opamp output and R2.
(This is sufficient because the loading effect of R2 can be neglected).
What YOU did in your simulation arrangements was to place the test source between R1 and ground!
As a result, you get the transfer function of the corresponding inverting amplifier model - but NOT the loop gain.
Both transfer functions will, perhaps, exhibit a similar phase response, however, the magnitude - and hence, the point where we find the phase margin -  will be not the same.
Do you now understand my concern?

[MrAl]

Hello again,

Yeah that doesnt look right to me either.  Not only is the perturbation signal NOT in the feedback loop, it's in the non inverting input circuit which unless there is another inversion somewhere that will produce a gain that is higher than what it would be if it was in the inverting input circuit, unless of course the gain was very high where the extra gain did not matter that much, but then i would have to question, why bother doing it that way.

My suggestion is to START with a simpler circuit where we can actually calculate the gain and whatever else is needed more easily than with this circuit.  That way you can check the calculations with the simulation and make dahm sure they are the same.  I would say even the simplest circuit would prove or disprove your concept of how to do this, but if you want to keep this circuit you could probably change the mosfet to a voltage controlled source of some kind and that would make the theoretical calculations simpler.  Once you know you are doing it right, then you can go back to the 'real' circuit.
But as i said, even a circuit that is much simpler would help to prove your concept of how to do this, so you dont even have to start with this circuit you can start with another circuit which is easier to analyze theoretically. If you dont get the same results with the calculations as with the simulation, then you know you are doing something wrong.  Once you get the simpler circuit right then you just carry over the technique you used to the more complicated circuit.

[not1xor1]

It is sometimes still done this way, despite of not being a good solution. A good solution would be making the output stage capable of 2 quadrant operation and this way ensure a minimum speed of response at all currents, even negative.

I was planning to make it almost 2 quadrant (with the current sink branch working like a class AB audio amp)

unfortunately the current sink doesn't work when the output voltage is less than 1-1.5V (BJT darlington o sziklai pair) or a bit less in case of mosfet

BTW I googled for a standard way of measuring transient load response, but I got the feeling that everybody is doing it their own way regarding load steps (10/90%, half/full load, .1A/full load, etc) and regarding rise/fall time...
what droop/overshot values are considered acceptable?

any advice? (should I start another thread ?)

[not1xor1]

Hi,

I am not fan of this circuit. These are the main elements in the control loop, as shown.

1) there is a pole that comes from the op-amp. This contributes 90 degrees of phase shift.

2) the transconductance of the MOSFET, results in a current source, which forms another low frequency pole with the output capacitor.

Combined we have a low frequency double pole. This can be seen on the loop gain plots as a slope of -40dB/decade.

There is also a zero formed by the ESR of the output capacitor. It is this zero from the ESR that is keeping the loop stable.

Regards,

Jay_Diddy_B

what about using a separate opamp to generate a 0-maxVout reference voltage (GND referenced) and using a floating voltage follower opamp as voltage regulator while keeping a floating reference voltage and opamp as current regulator?

[Jay_Diddy_B]

I still don't understand your concern. Consider these models:

Jay_Diddy_B, you don`t understand my concern?
For clarification, we do not need new or modified models.
You only must answer my question:
Is the ac test source in all three simulation schemes (post#7 and your last post) inside the feedback loop?
Obviously, the answer is NO!
Instead, these sources are grounded and the loop is still closed. This is the result of a simple visual inspection and cannot be denied.   
Hence, all of your simulation results might be identical - but neither shows the correct loop gain.

For illustration purposes, Let me discuss a simple example:
Consider the classical non-inverting opamp amplifier (feedback chain R2-R1, with R1 connected to ground.)
For testing the loop gain, we open  the feedback loop and place a test source BETWEEN opamp output and R2.
(This is sufficient because the loading effect of R2 can be neglected).
What YOU did in your simulation arrangements was to place the test source between R1 and ground!
As a result, you get the transfer function of the corresponding inverting amplifier model - but NOT the loop gain.
Both transfer functions will, perhaps, exhibit a similar phase response, however, the magnitude - and hence, the point where we find the phase margin -  will be not the same.
Do you now understand my concern?

I believe I have the injection source in the correct position.

Here is a picture, from the Picotest website that shows how to use a signal injector:



Here the injector is placed above the top resistor and the signals are measured with respect to ground.

Here is the original posters schematic, redrawn to put the parts in the conventional places:



The injector is definitely inside the loop, it is at the top of the divider, consistent with the Picotest website.

If I do this transformation, and move the reference voltage, the circuit is even closer to the Picotest schematic.




What YOU did in your simulation arrangements was to place the test source between R1 and ground! - Not True from a small-signal point of view. Because the circuit is floating I can swap the ground and the output nodes:



I still have the same circuit.

Regards,

Jay_Diddy_B