Memory Questions converting 16X4 to 32X4 & 32X8

[StevenSeagal]

If someone can guide me along here and let me know if I'm on the right path. Let me start by saying I am a beginning CE student and have made sense of everything I have dealt with this semester up to sequential logic which seems to be throwing me for a loop no pun intended. I know this is too general of a statement, and to narrow things a bit further I'm having difficulty implementing some circuits on paper.

I have gone through some of the free material here along with text book and back over lecture notes etc. and still feel a bit unsure as to how to attack circuit problems. Most of the individuals on the forum seem to be gurus in this field and any advice you might offer would be greatly appreciated.

Now for my questions in particular, I can get my drawings up to help make more sense of things if just listing how I plan on going about things is a bit hard to picture.

First: I have 74F189 (X2) chips along with a decoder and need to convert these 3 into a 32X4 RAM circuit.
My thoughts: I will have a 3-to-8 decoder with inputs A0, A1, A2. And outputs running to A0, A1, A2, A3 on the first chip & the remaining 4 outputs from the decoder running to A0, A1, A2, A3 on the second chip. Connect the data lines D0 with D0, D1 with D1, D2 with D2, D3 with D3 from the first chip to the second and similarly connecting the data outputs in a similar fashion O₀ with O₀, O₁ with O₁, ...

Second: I have 74F189 (X4) chips along with a decoder and need to convert these 5 into a 32X8 RAM circuit.
My thoughts: Much like above although this time I will use my 3-to-8 decoder with inputs A0, A1, A2. And outputs running to A0, A1, A2, A3 on the first/second chip & the remaining 4 outputs from the decoder running to A0, A1, A2, A3 on the third/fourth chip. Connect the data lines D0 with D0, D1 with D1, D2 with D2, D3 with D3 from the first chip to the second and similarly connecting the data outputs in a similar fashion O₀ with O₀, O₁ with O₁, ... I will connect the data lines D0 with D0, ..., D3 with D3 from the third chip to the fourth and similarly connecting the data outputs in a similar fashion O₀ with O₀, O₁ with O₁, ...

Any thoughts on any of this would be greatly appreciated. And again I can get pictures of my designs if it will make things a bit more clear on how I plan on going about these circuits.

[Rufus]

The chips are 16x4.

To get 32x4 one chip needs to do half the addresses and the other chip the other half. One address line needs to choose which chip is enabled. It doesn't matter which address line but usually the most significant is used. The other address and data lines are common to both chips.


32 x 8 is just 2 32x4 circuits.

[grumpydoc]

This is an exercise, I presume?

The correct answer is, of course, that the 74F189 is a terribly obsolete beast and if you really want a bigger SRAM just go and buy one.

Being more helpful - each RAM has 16 4 bit locations selected by 4 address lines (A₀ to A₃). You want 32 locations selected by 5 address lines (A₀ to A₄). Think about how to map the 32 location address space onto the two chips.

Your suggested solution has an obvious flaw - you only have three address lines to select locations in the RAM chips - therefore you can only ever select one from 8 locations.

[StevenSeagal]

Thank you Rufus & Grumpy

The chips are 16x4.

To get 32x4 one chip needs to do half the addresses and the other chip the other half. One address line needs to choose which chip is enabled. It doesn't matter which address line but usually the most significant is used. The other address and data lines are common to both chips.

32 x 8 is just 2 32x4 circuits.

There was a hint that just an inverter was needed to make the 32x4 circuit but to still use a decoder. It sounds like what you're describing is more along the lines of what I should be doing on this circuit and focusing more on a signal that gets switched out to CS & WE on the chips, while still connecting my data lines & output data?

This is an exercise, I presume?

The correct answer is, of course, that the 74F189 is a terribly obsolete beast and if you really want a bigger SRAM just go and buy one.

Being more helpful - each RAM has 16 4 bit locations selected by 4 address lines (A₀ to A₃). You want 32 locations selected by 5 address lines (A₀ to A₄). Think about how to map the 32 location address space onto the two chips.

Your suggested solution has an obvious flaw - you only have three address lines to select locations in the RAM chips - therefore you can only ever select one from 8 locations.

Yes this is an exercise, and that makes sense but I still feel like I'm doing a bit of guess work when I should see these things clearly. Considering one chip I have 4 address lines (A₀ to A₃), now if I want to have access to 32 locations I understand that I need 5 address lines. But how do I work this out using a decoder. Say for instance using the 4 chips and a decoder if I use a 5-to-32 bit decoder I only 16 (4 address lines*4chips) to make my connections. Also what do I need to consider with my CS & WE when making my design?

[grumpydoc]

Yes this is an exercise, and that makes sense but I still feel like I'm doing a bit of guess work when I should see these things clearly. Considering one chip I have 4 address lines (A0 to A3), now if I want to have access to 32 locations I understand that I need 5 address lines. But how do I work this out using a decoder. Say for instance using the 4 chips and a decoder if I use a 5-to-32 bit decoder I only 16 (4 address lines*4chips) to make my connections. Also what do I need to consider with my CS & WE when making my design?

Given that this is an exercise it is better if you figure it out.

Rufus has basically given you the answer, also the comment about "just an inverter" is correct.

You have two chips with half of the data, focus on how to decide which of these holds the address you want to access. Think about how the CE lines work

[Rufus]

along the lines of what I should be doing on this circuit and focusing more on a signal that gets switched out to CS & WE on the chips, while still connecting my data lines & output data?

With CS inactive the chip can not be written to and its outputs remain tri-state (open circuit). Any number of chips (within reason) can be connected with common address, data, and WE signals as long as only one is selected at a time.

[StevenSeagal]

Given that this is an exercise it is better if you figure it out.

Rufus has basically given you the answer, also the comment about "just an inverter" is correct.

You have two chips with half of the data, focus on how to decide which of these holds the address you want to access. Think about how the CE lines work

I appreciate this, I have for my first design with the 32x4 a 1-to-2 decoder with an input that in a sense acts like my A₄ in a A[4:0] and the outputs will run to the corresponding CS for 16 4 bit locations on the first chip and extending onto 16 4 bit locations on the second chip depending on the A₄ supplied into my 1-to-2 decoder. And working out the 32x8 will combine my A₀, A₁, ... out from my chips.

With CS inactive the chip can not be written to and its outputs remain tri-state (open circuit). Any number of chips (within reason) can be connected with common address, data, and WE signals as long as only one is selected at a time.

I appreciate this, the CS is where I wasn't focusing on initially. I was trying to have my decoder handle the assigning as opposed to leaving that to the addressing lines.