MOSFET drain current spec

[electrolust]

I see that the FET seems to switch off like a capacitor charging / discharging with that nice curve.  Not at all like the multi-linear trace I had a few posts earlier, where my grounding was a bit suspect.

Actually no, it's still multi-slope linear, but with the transitions roughly exponential.  I didn't have the timescale zoomed out far enough to see that it was still linear.

I found online refs that inductance at the gate was a problem and a gate resistor would fix it.  I added R_G(EXT) 4k7 and that fixed the larger oscillations somewhat.  Now I have a ringing at the point that I shut off the gate voltage, and I wonder is that a probing issue or real.

I just wanted to give a quick update.  As I learn more about this and see how the other FET parts compare with and without resistor, I'll post further updates here.

[radiogeek381]

Great work!

As you can see in the last set of traces (reply from Mar 1 at 1053) there is a bit of "wiggling" on the gate terminal that mirrors the wiggle on the drain terminal.  This is caused by the Cdg capacitor that couples the falling drain voltage to the gate and pushes it down a bit.  When this happens, Vgs drops, thus making Vds rise, which couples back to the gate terminal through Cdg and the cycle repeats.   

In pathological cases, this can go on for many (damped) cycles.  I'm looking at a very inexpensive boost converter this week that rings at 156MHz for precisely this reason. 

There are three ways to mitigate this effect.

• use a device with a lower Cdg
• use a lower impedance driver into the gate terminal
• load the drain terminal so much that the Vds edge rate is very very slow
• load the gate terminal with lots and lots of extra capacitance to both slow the edge and
  reduce the amplitude of the feedback. (Vds acts on Vgs through the voltage divider formed
  by Cdg and whatever capacitance is between gate and source.)

Item 2 is what I meant when I suggested a "stiffer" driver a few weeks ago.

As for gate resistors for killing the oscillations from inductance in the gate, source or drain leads, I'd be loathe to put a resistor in series with the gate, but putting it from gate to ground might not hurt.  I suspect the folks who suggest that are looking to the idea of increasing circuit losses by dumping energy into the resistor.  (This is another way of looking at damping.)  I'd much rather be in a place where I'm not getting zorched by the lead inductances in the first place. 

Again, you can avoid that kind of problem in at least two ways. A) keep all the leads really really short and make sure you have a good solid uninterrupted ground plane under all the interesting bits, or 2) use a device that has no gain at frequencies higher than is useful. 

The same great advances in technology that have brought us really high gain devices that work into the GHz range also brought us parts bins that are full of high gain devices that work into the GHz range.  Every once in a while we grab one of those to control an LED.  If you're flashing your LED at 300 MHz and you can notice it, then it may be time to cut down on the coffee intake.

[electrolust]

new thread started https://www.eevblog.com/forum/beginners/fet-gate-inductance-and-oscillation/