MOSFET drain current spec

[electrolust]

I'm looking at a specific part, NXP PMV20XNEA http://www.nxp.com/documents/data_sheet/PMV20XNEA.pdf .  Fig. 6 of the spec sheet shows drain current as a function of Vds.  You can see on the Vgs=2.3V and above curve, that the curve ends before reaching Vds=3.3V.

I'm using this part as a low side switch with an LED and current limiting resistor, with Vds near 0V.

1. How am I to interpret the curves that end at lower Vds?  That the current is at least the max value, or that such voltages are not supported at all?

2. As Vds goes lower, Id goes lower.  I understand the Id value to be the maximum current that can be carried.  Does that mean my Vds may actually be too low, as lower Vds results in lower Id?

My simple circuit is VCC=3.3v, to a 68r resistor, to an LED (2.0V drop), to the MOSFET (D), to ground (S).  Vgs is also 3.3V.

[radiogeek381]

Great question!

OK.  Here's the big central takeaway:  For devices like MOSFETS, BJTs, JFETs, Diodes, wobulators, or anything else
with a non-linear response (and even for things that are linear) the currents through their branches and the voltages
between their terminals must satisfy a few physical constraints.  (I know, I'm starting from the bottom here, but please
bear with me.)  The constraints are:
1. Energy must be conserved.  (No free lunch.)
2. Net current into a node equals net current out of a node.
3. The sum of the voltages in a loop must add to zero.

That's step one. 

So, let's imagine that you've got the source of your PMV20XNEA connected to ground
The drain is connected to terminal A of a 0.5 ohm resistor.
The other end of the 0.5 ohm resistor is connected to +5V relative to ground.
The gate is connected to a voltage source whose negative terminal is connected to ground.

What figure six says is that for a Vgs of 2.0 V, for instance, the current will rise linearly up to
about Vds = 0.3 volts or so.. (this is not a magic number, I'm just looking at the graph.)  Up to this
point the device looks like a resistor between Drain and source -- the current is proportional
to Vds (in fact it looks kinda like a 0.03 ohm resistor -- Sure enough, when I look at RDSon the
spec'd value is 24 mOhms -- not bad for eyeballing it.

The thing that is making the current flow from source to drain is the electric field caused by
the potential applied between drain and source.  As the gate voltage rises wrt the source, it
draws carriers into the channel that can then be swept across from source to drain.

But then something happens.  At around 0.5  volts, the current density in the channel and the
voltage drop across the channel creates a bottleneck near the drain terminal -- At this point
you don't get that much more current even as the drain-source potential rises.  The device is
in saturation. This is Idsat.  For this device the saturation current at Vgs = 2.0 is about 12 A.
(holy cow! 12A!) 

Oooh... but remember that 0.5 ohm resistor.  If we drew 12 Amps at that point, the drain voltage
would be 5V - 0.5 ohms * 12A or -1 volts.  That can't be right.

And it isn't -- What happens is that the constraints on the device and the laws of nature make the current and voltage
in the circuit "work out".

So let's look at the constraints:

(1) Id flows through the device and through the resistor.

(2) Vds = 5V - Id * 0.5 ohms
we can't change that -- kirchoffs voltage law.

(3) We also know that Ids = K * f(Vgs,Vds) 
where f is some function of the gate-source and drain-source voltage.

Vgs is fixed (we said that it would be 2V at the start of this example.)
Vds and Id must solve the constraints from equations 2 and 3.

We could resort to expanding the function of Vgs and Vds -- and you
should look it up at some point.  But we can also "solve" this by looking
at the graph.

Add one line to the graph.  It starts at VDS = 5V, Ids = 0
It ends at VDS = 0V and Ids = 10A.
This is called a "load line"   It represents all the possible values
of current through the 0.5 ohm load resistor, and the Vds voltage
that would result.

So now we have this load line and the current through the device
MUST lie on that load line.  That's the constraint from equation 2.

But Ids, Vds must also satisfy equation 3.  That equation is shown
as the Vgs = 2.0 V curve in the middle of Figure 6. 

The load line intersects the Ids curve at about 9Amps and 0.4V.

The device is in the linear region. 

Now imagine that the load resistor was just 0.25 ohms.  Then our load
line would go from Vds = 5, Ids = 0 to Vds = 0, Ids = 20

That would intersect the Ids curve at Ids = 12A and Vds = 2.0 V


I hope that helps.  A whiteboard would have been easier.

---73

[radiogeek381]

It took a while for the penny to drop.  There's a second usefull point to explore
here.

So this device you're using is going to switch an LED load.  A single LED?
That's 10 mA to 20mA.  The MOSFET is built as a power switch and
is typically used in applications where it's could be dissipating 5W or so
on a big heat sink.  It's continuous operating drain current should be
limited to about 4A, but that still makes it much bigger than you need
for an LED.

And it is much bigger than you want.

It is tempting to pick the biggest hammer in the toolbox, but if
you're doing watch repair, a 16 pound sledge is probably not
the best choice.

Here's why:

1. Look at the spec for Ciss in table 7.  The cap looking into the
gate terminal is 930 pF on a typical device.  This is really honking
huge.  That's reflectedin the Qg(tot) with a max of 15nC.  At 1mA
of driver current you're going to take 8 microseconds to bring
the gate to 2V.  Probably not all that bad, but there's more.
(I see from fig 14 that the typical Qg at Vgs = 2V is about 4nC.
That brings the rise time down to 4 uS or so.)

2. The Crss is a capacitance from drain to gate.  That's not reflected
in any of the steady state DC curves showing Id vs Vds,Vgs.  And that's
where we can see some real trouble.

Imagine that the device is ON --  Vds about 0 (since we're only drawing
10mA against an Rdson of 30mohms -- Vds is about 0.)  Vgs is 2 volts
or so. 

Now we pull Vgs down with a pulldown that can sink 10mA.  It's going to fall
in about 200 nSec.   That's not too slow, not too fast. 
But at the same time, the drain is rising.  Fast.  and it's got about 144pF
between it and the gate.  That's going to want to pull the gate voltage UP.

Which will cause the drain voltage to ... DROP! 

Which will couple through the 144pF cap to the gate and cause it to
fall.  Which will cause the drain voltage to RISE.  Which will .....

This oscillation doesn't go on forever, but it can swing through a
cycle or two.  It is a heavily damped oscillation that is really noxious
as it is very very broadband.  You'll hear it on just about any radio
nearby.

This, of course, can be ameliorated by stiffening up the gate drive
(in fact, that 10mA pulldown in the microcontroller isn't really a
10mA current source, it is pretty "soft" as a power source.)

3. Finally, I'll point you to figure 7. This shows "sub-threshold"
current as a function of Vgs.  It suggests that you really really
want to get the Vgs below 0.75 V as the leakage at that point
may be as large as 0.2 mA.  That might be enough to get a
faint glow out of the LED. 

4. Note that NONE of the curves shows the behavior of the
device at very low drain currents, other than the sub-threshold
curves.  Figure 12 suggests that at room temperature (this
device is going to run cooollll..) Vt (threshold voltage, the
value of Vgs where the device starts to enter its linear region)
is about 0.75 V.  That's a little low for a casual application, IMHO.


BTW, as you scan the "static" characteristics, do not be alarmed
by the Rg figure.  This is the resistance looking into the Ciss gate
cap.  It is not a resistance between gate and source or drain.

----------

Frankly, I'm surprised that the drain leakage current is as low as it
is.  I guess I'll have to look at more datasheets...

What you are doing is probably just fine.  But I wouldn't make a habit
out of using the biggest hammer in the toolbox.  There are better suited
and cheaper solutions.

[Fgrir]

1. How am I to interpret the curves that end at lower Vds?  That the current is at least the max value, or that such voltages are not supported at all?

2. As Vds goes lower, Id goes lower.  I understand the Id value to be the maximum current that can be carried.  Does that mean my Vds may actually be too low, as lower Vds results in lower Id?

I'll try shorter answers:

• Those curves end at lower Vds because you won't be able to get the Vds to rise any higher without destroying the part.  The curves stop at 25A which is the rated max peak drain current.
• That graph is not a maximum rating, it is the actual behavior of the device.  You want Vds to be zero when your FET is turned on, and that graph can be used to see what Vds to expect for a given Vgs and Id.

The important thing to understand is that curve applies when the FET is on, so your Vcc has nothing to do with the Vds in the graph.

[electrolust]

That graph is not a maximum rating, it is the actual behavior of the device.  You want Vds to be zero when your FET is turned on, and that graph can be used to see what Vds to expect for a given Vgs and Id.

huh.  I was reading it as X-axis (Vds) being the independent variable and the Y-axis (Id) being dependent.  ie, you somehow choose or determine Vds and it gives you Id.  But are you saying that I determine Id (say 20mA) and then read off what Vds will be?  And I should aim for lower Vds (by choosing higher Vgs) thus reducing power consumption, ie heat?

I still have to digest radiogeek's reply.

[Fgrir]

The graph shows the interrelation of the three variables so you don't have to think of any particular axis as dependent or independent.  If you know any two values the graph will tell you what the third will be.  So your conclusion is correct, although in this region you will probably get more use out of figure 8 that shows Rds(on) since you are way in the bottom-left corner of the figure 6 graph.
Of course you are so close to zero power dissipated in this particular FET that I wouldn't worry about it too much.

[HackedFridgeMagnet]

I'm looking at a specific part, NXP PMV20XNEA http://www.nxp.com/documents/data_sheet/PMV20XNEA.pdf .  Fig. 6 of the spec sheet shows drain current as a function of Vds.  You can see on the Vgs=2.3V and above curve, that the curve ends before reaching Vds=3.3V.

I'm using this part as a low side switch with an LED and current limiting resistor, with Vds near 0V.

1. How am I to interpret the curves that end at lower Vds?  That the current is at least the max value, or that such voltages are not supported at all?

2. As Vds goes lower, Id goes lower.  I understand the Id value to be the maximum current that can be carried.  Does that mean my Vds may actually be too low, as lower Vds results in lower Id?

My simple circuit is VCC=3.3v, to a 68r resistor, to an LED (2.0V drop), to the MOSFET (D), to ground (S).  Vgs is also 3.3V.

Hi
You said Vgs was 3.3V therefore the red curve is your output characteristic. (estimated between the Vgs 4.5 and the Vgs 2.5.)
At this point it is almost fully switched on and the equivalent of a resistor (because it has a linear relationship between voltage and current. ) The series resistance ( rds(on) ) is calculated as 0.5V/24amps = 21mOhms.

So when the FET is switched on you can model the operation of your circuit as just the original resistor in series with the LED in series with the 21mOhm resistance of the FET.

Because the FET has a nice low on resistance in this case you can really just assume the FET is a short circuit when switched on.

[electrolust]

Great question!

Thank you taking so much time with your very detailed reply.  I was following you all the way through to ...

What figure six says is that for a Vgs of 2.0 V, for instance, the current will rise linearly up to
about Vds = 0.3 volts or so.. (this is not a magic number, I'm just looking at the graph.)  Up to this
point the device looks like a resistor between Drain and source -- the current is proportional
to Vds (in fact it looks kinda like a 0.03 ohm resistor).
...
But then something happens.  At around 0.5  volts, the current density in the channel and the
voltage drop across the channel creates a bottleneck near the drain terminal -- At this point
you don't get that much more current even as the drain-source potential rises.  The device is
in saturation. This is Idsat.
...
Oooh... but remember that 0.5 ohm resistor.  If we drew 12 Amps at that point, the drain voltage
would be 5V - 0.5 ohms * 12A or -1 volts.  That can't be right.
...
So let's look at the constraints:

(1) Id flows through the device and through the resistor.

(2) Vds = 5V - Id * 10 ohms

Where did the 10 ohms number come from?

[electrolust]

(3) We also know that Vds = K * f(Vgs,Vds) 
where f is some function of the gate-source and drain-source voltage.

Also, how is that possible?  Vds is on both sides of the equation.

[radiogeek381]

(3) We also know that Vds = K * f(Vgs,Vds) 
where f is some function of the gate-source and drain-source voltage.

Also, how is that possible?  Vds is on both sides of the equation.

I'm sorry -- both the 10ohms and the Vds thing were typos...  I've fixed the
original post.

The 10 ohms should be 0.5 ohms ... (In the first draft, I picked 10 ohms
but it made numbers inconvenient for illustrating the load line....)

Ids = K*f(Vds,Vgs)

Thank you for pointing these out.

[electrolust]

I hope that helps.  A whiteboard would have been easier.

OK yeah after the corrections I worked through the rest of it and it was extremely helpful.  The load line really helps make sense of it all.  Now to get through your 2nd comment ...

[electrolust]

Figure 12 suggests that at room temperature (this
device is going to run cooollll..) Vt (threshold voltage, the
value of Vgs where the device starts to enter its linear region)
is about 0.75 V.  That's a little low for a casual application, IMHO.
...
What you are doing is probably just fine.  But I wouldn't make a habit
out of using the biggest hammer in the toolbox.  There are better suited
and cheaper solutions.

I actually selected this device based on the lowest Vt.  Because a generic 2N7002 has Vt = 2.5V but isn't specified for Vgs = 3.3V (spec starts at Vgs = 4.0V).  So I thought smaller Vt = better.

Why is choosing something with a small (/smaller) Vt not good?  I'm just now looking at Fairchild AN-9010 and it describes the ohmic (linear?) region as to the left of the Vgs-Vt line, ergo smaller Vt = larger ohmic region.  Is that itself not a good thing or is it that the other constraints that come with a smaller Vt are the things to watch out for?

The Ciss point you make is pretty interesting.  I think excessive noise will be a problem for me.

I also don't have a pulldown on Vgs.  I'm trying to drive it with a switch (not really, but for the sake of this discussion) AS WELL AS an MCU output.  So either/or can turn the LED on.  Now I realize I'll have to see what it means to apply a signal to an MCU pin in output mode.

When you say better and cheaper solutions, do you mean a different FET part or a different design altogether?

[electrolust]

I also don't have a pulldown on Vgs.  I'm trying to drive it with a switch (not really, but for the sake of this discussion) AS WELL AS an MCU output.  So either/or can turn the LED on.  Now I realize I'll have to see what it means to apply a signal to an MCU pin in output mode.

Oh.  Normally, the MCU does not turn on the LED (via the FET).  But, I do leave the LED (FET) pin in output mode.  I measured MCU ouput pin resistance to ground:

output LOW: 22.2r
output HIGH: 655k
MCU off: 46.5k

Does that mean that I should consider this as being equivalent to having a 22.2r pulldown resistor?

I guess this is 3.3/22 = 150mA of current, is that ok or might that present a problem due to heat as the gate "cap" discharges?  I wouldn't expect that the MCU is meant to serve as a pulldown that way.

[KL27x]

output LOW: 22.2r
output HIGH: 655k
MCU off: 46.5k

How are you calculating this? You can't directly measure resistance between an active output and anything else. Unless you have a new fancy DMM which please tell me where to buy this.

[radiogeek381]

I actually selected this device based on the lowest Vt.  Because a generic 2N7002 has Vt = 2.5V but isn't specified for Vgs = 3.3V (spec starts at Vgs = 4.0V).  So I thought smaller Vt = better.

Why is choosing something with a small (/smaller) Vt not good?  I'm just now looking at Fairchild AN-9010 and it describes the ohmic (linear?) region as to the left of the Vgs-Vt line, ergo smaller Vt = larger ohmic region.  Is that itself not a good thing or is it that the other constraints that come with a smaller Vt are the things to watch out for?

Short Answer:
IMHO, it is a good idea to pick the Vt that is a bit above the maximum output low voltage for the driver.
In the case of an Atmel 328, for instance, the Vol (output low voltage) at 10 mA is no greater than 0.6V at
an ambient temperature of 85C.  Yes this is at 10mA current draw, way more than you should expect,
but a conservative approach would suggest looking for a Vth somewhere near mid-rail. 

Long Answer:
In addition to the short answer's rationale: Low Vt makes it easier to turn the device on, but harder
to turn it off, and keep it off.  This device has pretty good sub-threshold leakage specs, but others
may not.

Your circuit will work.  And at $0.43 from Mouser in onesie-twosies, I'm tempted to buy a few for
the parts drawer.  But my go-to solution for turning on diodes indirectly from a MCU output is
a 2n3904 or its SMT equivalent.

• It is easy to drive,
• at 20mA it is only loafing along,
• the breakdown voltages are high enough that it is hard to blow them up in normal use (make sure you protect them from inductive loads though),
• has a base input cap of about 20pF (much closer to the load that most I/O pins are designed to drive)
• has a pretty good current gain even at low currents,
• and there are about 500 hundred of them in a drawer next to my desk .

So, how would I use it? Here's a wirelist:
(this is a list of component pins and the points to which they connect.
Each connection point has a name, like V+ for the power supply positive,
GND for the power supply negative...)

Component	Pin Name	Node Name
Battery	Pos	V+
Battery	Neg	GND
LED	Anode	V+
LED	Cathode	Rd
Rc	1	Rd
Rc	2	C
Q1	Col	C
Q1	Em	GND
Q1	Base	B
Rb	1	B
Rb	2	INPUT

So, now we want to calculate the values for
Rb and Rc. Let's assume that the input voltage
ranges from 0.7 for low, and 4.3 for high.
The supply voltage is 5V.
And let's say we want something like 2 volts across the
diode at about 10mA.

• The 3904 has a Vce(sat) of about 0.2V.  So we need to
  drop Vcc - Vdiode = Vce(sat) at 10mA.  (5 - 2 - 0.2)/10mA = 280 ohms.  Call it 270.
• We only need 10ma/hfe or about 0.2mA of base current. It isn't a good idea to design
  assuming anything about hfe other than it is probably bigger than the minimum.  Let's give
  ourselves a little margin and call it 0.3mA of base current, and we want 0.7V Vbe.
  (4.3 - 0.7)/0.3mA = 12000 ohms.... I have a bucket full of 10K resistors for just this
  purpose -- one of those will do fine.

At Vol, of 0.7V we have not a whole lot of current flowing.  (There is some, because
the base-emiter path is a diode, and it draws some current no matter what.) Assume
for the moment that this is a really magic 3904 that has a beta of 60 even when Vbe is
0.5V -- then we have 1mA through the diode -- it will probably glow very weakly, but
to do this we had to have a really really magic 3904 and an MCU that is really quite
at the edge of worst-case Vol.

If you wanted to use a switch as well as the MCU, I'd put a second 3904 next to
the MCU driven one.  But in this case, I'd run INPUT side of the second base
resistor to a switch connected to V+.  (and btw, you've just built a NOR gate
with resistor-transistor-logic.)

I hope this is helpful.  I would have written less, but there wasn't sufficient time.

[electrolust]

output LOW: 22.2r
output HIGH: 655k
MCU off: 46.5k

How are you calculating this? You can't directly measure resistance between an active output and anything else. Unless you have a new fancy DMM which please tell me where to buy this.

I recognize that the high output case is baloney, but it "measured" as such so I posted it.  The low output case is reasonable though, is it not?

[electrolust]

...
1. Look at the spec for Ciss in table 7.  The cap looking into the
gate terminal is 930 pF on a typical device.  This is really honking
huge.  That's reflectedin the Qg(tot) with a max of 15nC.
...
What you are doing is probably just fine.  But I wouldn't make a habit
out of using the biggest hammer in the toolbox.  There are better suited
and cheaper solutions.

Still trying to wrap my head around Ciss, Qg et al. but for a quick check, how does this part look?  Fairchild FDV301N http://media.digikey.com/pdf/Data%20Sheets/Fairchild%20PDFs/FDV301N.pdf $0.23 in unit qty, so half the price of the other part.  Only 9pF Ciss (100x smaller!) than the NXP PMV20XNEA I'd selected earlier.  Rdson is quite a bit more, but still small enough.  I'll just tweak the LED load resistor to suit.

[radiogeek381]

Nice choice.  Available, inexpensive, easy to drive.  Let's go through the checklist

-- for "absolute max ratings" ---
Vdss max is 25V -- no problem here. 
Vgs max is 8V -- the only reason you'd see a problem here is if
the MCU driving the line drove a very very sharp edge with a 5V swing
over a very long line.  Then you could get overshoot/ringing/reflection
at the far end.  But this isn't going to happen because the line length
would have to be several feet before this became a problem, and the
MCU is unlikely to drive that hard.

Id continous 0.22A -- plenty of head room for an LED

Pd -- at 0.35W we'll have to check that later, but at 20mA that lets
Vds rise to well above your supply (about 17.5V)  However, there's
another limiting factor for power.

Rtheta-jA -- this is the thermal resistance between the chunk o' silicon
and the air.  It is 357 C per Watt.  So, what does that mean?

Let's assume that the transistor is in still air (no fan, no convection).
But let's assume that the air remains at 25 C regardless of conditions.
The junction temperature is Ta + Rtheta-ja * P
or
25 + 357 * P
Let's let P be 0.35 Watts, the max spec. 
That puts the junction at 150 C.  That's a bit on the hot side, but not
outrageously so.  But note that the characteristic curves that show
variations with temperature all top out around 125 C.  That's a hint.
That says keep the temperature below that if possible.

Higher temperatures lead to lots of things, but most often, reduced
lifetime, higher leakage, crappier performance, disharmony in the
force, and the heartbreak of psoriasis.   As a comparison, big time
microprocessor designs for servers work hard to keep the die
temperature below about 105C, and it isn't because they're
cold blooded.

So, we probably want to keep the power dissipation below 0.1 W, to
give us a Tj of 60 C in our magic still air.   A heat sink helps, but not
as much as you'd hope.

---------------------------------

Now for the electrical characteristics.
Vth is nominally 0.85 with a min of 0.7 at low currents.  Ok...
The Idss (cutoff leakage current) for really high Vds is 10 uA.
Leakage is strongly dependent on Vds, so even if we have
a little noise on the gate, say 0.1 V, the LED isn't going to
glow much.

The device doesn't mind if Vgs is 5V, so we're covered there.

Now let's look at the curve families.  If Vdd is 5V and your LED drops
2V at 20mA, then we want to know what the Vds might be. 
An MCU driving this gate is going to pull it right to the top rail
pretty quickly (that's the advantage of the 9pF Ciss).  So we
can follow the Vgs = 4.5V curve.

Once again, we've got lots of head room in the Id department.
At 20mA, we're way down in the lower left corner of the graph.
Let's calculate a likely neighborhood for Vds.
<remembering at all times that the graph is labeled "typical" and so
we don't want to bet the farm on getting exactly what the graph says.>

So, when I look at this curve, I see that the Id vs Vds curve intersects
at 0,0 and at 100mA, 0.25V -- so 20mA gets us something near
0.05 V for Vds. 

0.02 A * 0.05V = doodly squat, well below our 0.1W happy point.

More importantly, all of the drop is going to be across the diode and
dropping resistor.  So, we need 3V drop across the resistor at 20mA,
ergo 150 ohms or so. 

----------------

Let's do some sanity checks. 

First, Figure  2 suggests an Rds(on) of about 0.7 ohms at Vgs = 4.5.
0.7 * 0.02 = 14mV.   This is smaller than our 50mV estimate, but not
in any important way.  But Figure 3 says we might want to derate that a bit
if we think the device is going to heat up.  It won't.

Finally, we look at Figure 9.  You may have heard folks here use the
term "SOA"  This is the "Safe Operating Area" -- it's a way of giving
us a hint of how close we are to cooking Si give the operating parameters.
In this graph we place our point at the Id we expect (0.02A) and convince
ourselves that Vds will never stray outside the box.  In this case, you aren't
really pulsing the device; you should use the DC limit.  At 20mA you can
get to about 17V (sound familiar?  we calculated this limit earlier.)  I
wouldn't run it at that point, and neither will you, since Vdd is 5V.

As important, if Id rises to 50mA, then you still have headroom all the
way to Vdd plus a bit.  So the device isn't likely to get too hot.

--------------------------

So the device ought to work just fine.

--------------------------

[KL27x]

I recognize that the high output case is baloney, but it "measured" as such so I posted it.  The low output case is reasonable though, is it not?

The 22R output impedance of output lo does, indeed, sound perfectly reasonable.*

But AFAIC you CAN'T directly MEASURE resistance between points in a circuit under power with a DMM. A DMM measures resistance by putting a high impedance voltage source at one end and measuring the drop at the other end. It has to do this on unpowered circuit to get a valid measurement. An active hi/lo output is defacto under power. So measuring resistance between a digital output hi and ground is not possible.

*Yeah, on further thought, as long as the output pin is unattached to anything else, I don't see why you can't measure resistance between output low and ground with DMM while under power. I presume this is a valid measurement, since there is no voltage applied between the two points, other than what the DMM puts through it (circuit here is the just the drain-source of the output low FET while on). Yes, this means that when output is lo, that it is like putting a 22.2R resistor between that node and ground. Conversely, while output is high, one could measure the resistance between it and the power rail. Not between it and ground. So know we know.

[electrolust]

I played around on the breadboard (with a 2N7002 part) and this ultimately led to what I hope is a better intuitive understanding.  And so obvious now.  Unless I'm wrong.    How does this sound?  It's pretty much a rehash of what has already been said here, but now in my own words.

First one has to understand both of Fgrir's responses (#3 and #5).  The PMV20XNEA Fig. 6 graph shows a relationship, not an X-YZ independent-dependent function.

So, if I have a voltage source (Vds), I can find Id.  If I have a current source (Id), I can find Vds.  Given that I have a resistor load, I essentially have a current source.  So I can consider the corresponding Vgs line to be a "load line" of sorts for the FET; the Vds/Id relationship must fall somewhere on that line.  Now if I add in the load line for my resistive load (current source), because all those things must be simultaneously true, the intersection will be the point of interest.

Lastly, it turns out that Vds/Id = Rdson when in the linear/ohmic region.  So if I'm in that region (Vgs-Vt > Vds > 0) I can do some easy math to figure out Vds, and thus get a quantitative understanding of how much power is being dissipated by the FET and by the load resistor.

So, if that's correct, why is it important for the FET (N-ch enhancement mode) to be on the low side?  Given that the same current flows through the entire circuit, it's not as if the FET sees a different current on low side vs high side.  We want Vgs-Vt > Vds, but given that voltage is differential, Vds is Vds regardless if the source terminal is at 0V or not.  So at least for an LED+resistor load there is no difference between low side and high side is there?

[radiogeek381]

I played around on the breadboard (with a 2N7002 part) and this ultimately led to what I hope is a better intuitive understanding.  And so obvious now.  Unless I'm wrong.    How does this sound?  It's pretty much a rehash of what has already been said here, but now in my own words.

-------------- SNIP --------------------

Lastly, it turns out that Vds/Id = Rdson when in the linear/ohmic region.  So if I'm in that region (Vgs-Vt > Vds > 0) I can do some easy math to figure out Vds, and thus get a quantitative understanding of how much power is being dissipated by the FET and by the load resistor.

So, if that's correct, why is it important for the FET (N-ch enhancement mode) to be on the low side?  Given that the same current flows through the entire circuit, it's not as if the FET sees a different current on low side vs high side.  We want Vgs-Vt > Vds, but given that voltage is differential, Vds is Vds regardless if the source terminal is at 0V or not.  So at least for an LED+resistor load there is no difference between low side and high side is there?

Good job!   Your understanding is getting there. 

So, to the last question.  The arrangement you've described is called a "source follower." 
(There is a similar arrangment for BJTs called an "emitter follower.")

Note that in this case, Vs (the voltage on the source) is determined by the current
flowing in the load.  Let's assume for the moment that your goal is 20mA through
a 2V diode, with no series resistor (you wouldn't do that, but it is a useful simplification
for now.) 

So Vs is 2V, Vd is VCC (we've been assuming 5V. Let's say that Vg is 4.5.

So Vgs is 4.5 - 2 or 2.5V.  Vds is 3.

Take a look at the curve in Figure 1 here https://www.diodes.com/assets/Datasheets/ds11303.pdf
We're way down at the bottom (the 2n7002 has a very convenient Vth for a pulldown device -- right in
the middle of a 5V logic swing, but is not so good as a source follower).    We're way down at the bottom
of the figure, but you can see we're on the "flat" part of the Id vs. Vds curve -- the device is in saturation.
Rds(on) doesn't apply here because we're not in the linear region. 

Of course, the actual Vds and Vs (voltage at the source, hence voltage across the diode) will be determined
by a reconcilliation of the diode's I-V curve and the FETs Vds,Vgs,Id curve.  Adding a resistor to provide one
more constraint might help improve the predictability of the diode current.  As it stands, without the resistor
you're reconciling two chunks of silicon that both have complicated relationships with temperature.

-------------

Let's look at your other goto device, the FDV301N.  With its lower Vth, it is an interesting choice for a
source follower.  Let's see why.

Assuming the same conditions:
Vs = 2V.  Vg = 4.5, Vd = 5.

Now Vgs = 2.5 V and Vds = 3V. 

Let's look at the curve in Figure 1 of http://media.digikey.com/pdf/Data%20Sheets/Fairchild%20PDFs/FDV301N.pdf

Hot diggity!  For once, we're on a useful part of the curve!

The curve in figure one says that our drain current is about 300mA.  (Follow the 2.5V Vgs curve
all the way to where it intersects Vds = 3V.)

Well, that can't be right.  If we tried to put 300mA through an LED it would emit light, but
not for long. (All diodes are light emitting diodes if you try hard enough.)

The problem, of course, is that your source follower is a voltage source.  Apply excessive
voltage to a diode and you get what the diode doesn't deserve.   Yes, the actual current
will not be 300mA, but it will be too high. 

So, let's put a resistor in series with the diode.  We've decided the diode voltage is going
to be about 2V for sane operation.  Let's make that assumption for now.

Let's also assume that no matter where we are on the Ids curve, the Id is going to be
predominantly determined by Vgs -- that is, we're in FET saturation. 

Take a look at Figure 5.  This shows Id vs. Vgs for a constant Vds.  Now as long
as we're in saturation, the Vds doesn't matter much. (Notice how "flat" the curves
are in figure 1?)

In this case Vg is pegged at 4.5 volts, because we stipulated that at the beginning.
What we want to find is Vs. Our 20mA point is somewhere about mid-way between
0 and 0.05 on the vertical axis.  We draw a horizontal line through that.  It will
intersect the Vgs line at about 1.25V plus or minus, depending on temperature.

That says that our Vs is Vg - 1.25 or 3.25V. 

We need to drop 1.25 volts across the series resistor we just added (Vs - Vdiode)
and we want the current to be about 20mA. 

R = 1.25 / 20e-3 = 62 ohms or so. 

Let's check our assumptions.  Are we still in saturation?  Vgs = 1.25 V, Vds =
5 - 3.25 = 1.75 V.   Looking at the curve in Figure 1, we're way down at the
bottom of the graph, but we're clearly in the saturation region. 

Source followers are useful.  For reasons buried in the mists of time, typically
we use pulldowns to drive loads like FETs.  Some have suggested it has to do
with NFETs being easier to manufacture, or the higher mobility of electrons vs
holes, or something else fundamental to the physics.  I don't believe it.

This pattern was well established by the late 60's, well before the advent
of commodity CMOS.   I suspect the genesis was that it is easier to think
of a transistor (FET or BJT) as a switch and just be done with it. 

[electrolust]

I've finally been able to revisit this.

1. Look at the spec for Ciss in table 7.  The cap looking into the
gate terminal is 930 pF on a typical device.  This is really honking
huge.  That's reflectedin the Qg(tot) with a max of 15nC.  At 1mA
of driver current you're going to take 8 microseconds to bring
the gate to 2V.  Probably not all that bad, but there's more.
(I see from fig 14 that the typical Qg at Vgs = 2V is about 4nC.
That brings the rise time down to 4 uS or so.)

2. The Crss is a capacitance from drain to gate.  That's not reflected
in any of the steady state DC curves showing Id vs Vds,Vgs.  And that's
where we can see some real trouble.

Imagine that the device is ON --  Vds about 0 (since we're only drawing
10mA against an Rdson of 30mohms -- Vds is about 0.)  Vgs is 2 volts
or so. 

Now we pull Vgs down with a pulldown that can sink 10mA.  It's going to fall
in about 200 nSec.   That's not too slow, not too fast. 
But at the same time, the drain is rising.  Fast.  and it's got about 144pF
between it and the gate.  That's going to want to pull the gate voltage UP.

Which will cause the drain voltage to ... DROP! 

Which will couple through the 144pF cap to the gate and cause it to
fall.  Which will cause the drain voltage to RISE.  Which will .....

This oscillation doesn't go on forever, but it can swing through a
cycle or two.  It is a heavily damped oscillation that is really noxious
as it is very very broadband.  You'll hear it on just about any radio
nearby.

Should I be able to see this on a scope?

I put 3.3V across my LED.  Then that connects to the drain terminal, which is also where I'm probing with the scope.  I have my function generator set for 3.3V pulse, 8.4ns rise/fall time (its fastest), connected to the gate.  I'm triggering on falling edge of the gate.

Here's what I get.  You can see the noise, which is greater on the PMV part than the 2N7002.  I'd question whether that's really noise or an artifact but you can see the clean portion of the trace so I think that's real noise.

What's also got me wondering, is why are the traces so similar?  The Ciss/Crss numbers are very different for these 2 parts.  Even ignoring the noise, I'd think the DS voltage should settle much much quicker with the 2N7002.

I've yet to test my FET of choice, the FDV301N.

This, of course, can be ameliorated by stiffening up the gate drive

Meaning, being able to supply more current?  How would I accomplish that?

[electrolust]

Ignore those traces.  The way I was grounding the probes was introducing lots of noise.  I was using another channel and using a test lead on that channel over to the power supply.  Instead of grounding the probe at the FET S terminal.  It's much less noisy if I use a probe ground clip at the S terminal.  I will post new traces in a little bit.

[electrolust]

OK let's try this again.

Here's 2 traces (1 zoomed) of an external sig gen and the DS voltage source off.  It's much cleaner than the previous trace but still a tiny bit of periodic noise.  It's for the PMV part per post #1.

I'd initially tried to use the internal generator on my scope for the GS voltage, but I saw that it affected the DS voltage.  So I switched to an external generator, think that the generator and scope functions have bad crosstalk.  But I see the effect is still there so maybe I will try again, to see if I can get the noise down a bit more.

Questions:

1. Why does V_DS drop below 0, and stay there, when V_GS drops to 0?
2. Sig Gen is set for 8.4ns fall time.  Why does it take 182ns?  Is this the effect of gate capacitance?
3. Are the couple of upticks in V_DS and V_GS the oscillation per radiogeek?

[electrolust]

And here are the traces with the DS voltage source on.  VCC -> LED -> DRAIN -> SOURCE -> GND.  Current limited to 20mA.  (I guess that makes it a current source, not a voltage source?)

Like the prior post, both of these traces are the same event, it's just one is zoomed in.

I see that the FET seems to switch off like a capacitor charging / discharging with that nice curve.  Not at all like the multi-linear trace I had a few posts earlier, where my grounding was a bit suspect.  At the 100us timescale, it looks nice albeit slower than I'd expect.  At the 1us timescale it looks awful.  Is that the oscillation effect as radiogeek describes?

Note that the fall time is 20% higher than it was with DS power off.  (180 vs 220 ns)


I'll try again with the FDV and 2N7002 parts asap.