[SOLVED] MOSFET gate voltage higher than voltage at drain/source. Safe?

[GarthyD]

I am wondering if there are any considerations or issues to be aware of when using a voltage at the gate of a MOSFET to switch a smaller voltage.

Two specific examples:

- Using a 5V signal at the gate of a P-channel MOSFET as a power switch to pass 3.3V, where both the drain and source are connected to components that are not tolerant to 5V.

- Using a 5V signal at the gate of a N-channel MOSFET that connects a load to ground, where the load consists of multiple devices operating on 3.3V that are not tolerant to 5V.

If there are issues, are there workarounds?

[AndyC_772]

Any MOSFET will have a maximum VGS rating which must not be exceeded, and which you can find by checking the data sheet.

Typically the gate can have either polarity with respect to the other terminals. There's no diode or other parasitic component between the gate and source or drain.

Short answer: there's no problem, go right ahead.

[Ian.M]

However if the  MOSFET breaks down for any reason, there is a high probability of a gate-channel short, so don't overload it and make sure there is an adequate snubber or clamping if switching an inductive load.

[tron9000]

There's no diode or other parasitic component between the gate and source or drain.

For this case: true
technically: there is a tiny bit of capacitance, but nothing to worry about

[GarthyD]

Any MOSFET will have a maximum VGS rating which must not be exceeded, and which you can find by checking the data sheet.

Typically the gate can have either polarity with respect to the other terminals. There's no diode or other parasitic component between the gate and source or drain.

Short answer: there's no problem, go right ahead.

Ahah! I was wondering what the heck VGSS was, why it was important, and why it is typically so large. So basically, I just have to stay in the range specified. This will help immensely.

Thankyou.

However if the  MOSFET breaks down for any reason, there is a high probability of a gate-channel short, so don't overload it and make sure there is an adequate snubber or clamping if switching an inductive load.

Thanks. I'll keep those things in mind, particularly if the gate is connected indirectly to somewhere untrustworthy.

For this case: true
technically: there is a tiny bit of capacitance, but nothing to worry about

Glad to hear it.

Thankyou all. Having this knowledge, especially a precise range based on component, is going to be extremely helpful. There is a section in the circuit I am working on that needs reworking, and this is probably going to buy me some much needed extra space.

[AndyC_772]

VGS (max) is usually around +/-10V to +/-20V for a small FET.

Just be aware that exceeding this specification, even briefly, can permanently damage the device. FETs are quite robust when it comes to handling short term overload conditions, but if the gate oxide layer is damaged, it's toast.

[GarthyD]

VGS (max) is usually around +/-10V to +/-20V for a small FET.

Just be aware that exceeding this specification, even briefly, can permanently damage the device. FETs are quite robust when it comes to handling short term overload conditions, but if the gate oxide layer is damaged, it's toast.

Thanks for the warning. I'll be sure to keep within the limits.

[suicidaleggroll]

VGS (max) is usually around +/-10V to +/-20V for a small FET.

Just be aware that exceeding this specification, even briefly, can permanently damage the device. FETs are quite robust when it comes to handling short term overload conditions, but if the gate oxide layer is damaged, it's toast.

Thanks for the warning. I'll be sure to keep within the limits.

And just FYI for future designs that might approach the maximum Vgs, a zener diode of the appropriate voltage works great for clamping it to a safe level.

[Zero999]

VGS (max) is usually around +/-10V to +/-20V for a small FET.

Just be aware that exceeding this specification, even briefly, can permanently damage the device. FETs are quite robust when it comes to handling short term overload conditions, but if the gate oxide layer is damaged, it's toast.

Thanks for the warning. I'll be sure to keep within the limits.

And just FYI for future designs that might approach the maximum Vgs, a zener diode of the appropriate voltage works great for clamping it to a safe level.

Yes, a zener will protect the gate from being zapped but beware that, if the zener conducts, whatever is connected between the source and 0V might get zapped with a higher voltage, than expected.

[amyk]

Safe, yes. In fact, absolutely necessary if you're doing high-side switching with an NMOS and want the output to go all the way to the rail. In fact, this is what the +12V supply for early triple-voltage NMOS ICs (which otherwise operated at +5V) is for --- to ensure that the outputs reach full voltage, instead of stopping at one threshold below (and the -5V is for the substrate or back-gate.)

[GarthyD]

Apparently I *didn't* have notifications on for this post. Sorry about the slow reply.

And just FYI for future designs that might approach the maximum Vgs, a zener diode of the appropriate voltage works great for clamping it to a safe level.

Cheers, thanks for the tip.

Safe, yes. In fact, absolutely necessary if you're doing high-side switching with an NMOS and want the output to go all the way to the rail. In fact, this is what the +12V supply for early triple-voltage NMOS ICs (which otherwise operated at +5V) is for --- to ensure that the outputs reach full voltage, instead of stopping at one threshold below (and the -5V is for the substrate or back-gate.)

Ah, of course. I've only recently started looking into this, partly because it didn't make a lot of sense until I understood the answer to my question at the start of the thread. Thanks for mentioning it.