You can model combinatorial logic in a CPLD or FPGA. What you probably can't do is make sequential circuits operate asynchronously. I would think that state machines are out of the question. I know a fellow who tried to reinvent a CPU using asynchronous logic but he ultimately failed. In the old days of transistor logic, gate delays were long and easier to deal with. A lot of timing was done with wire length.
An ALU, itself, is a combinatorial block, no problems with it being asynchronous. Registering the output is a different matter.