MosFET Transistor Pad Footprints

[Falcon69]

How come, on almost all the dual mosFET and Transistor chips I see, when looking at the data sheet and it's recommended pad footprint, it does not show the collectors and drains connected together with the pad in the center of the chip?

Like the ones listed in this data sheet for example. 

http://www.mouser.com/ds/2/302/PBSS4230PANP-354962.pdf

Is there a reason why the recommended pad footprint for SMD reflow soldering isn't connecting pins  6 & 7 (collector of TR1)?  Or are they just connected via a trace during the PCB layout? WHy not just make the pad (and the chip) show it as one big pad for both?

[ovnr]

... because that package may be used for other things, and manufacturers like recycling things?


Just connect the relevant pads together on your board. This is just another case of "Well that's just how it's done".

[Falcon69]

SO, for that particular chip, or other chips identical, it's merely a reuse of another package that may be used for a different application where those middle pads serve a different purpose and are actually another unconnected pin-out/in?

Like which chip? I am not sure I have stumbled across one where that those middle pins are different and not connected to one of the outer pins internally.

It's not a big deal. I was mainly just interested to see if maybe it was for heat dissipation during reflow or perhaps it was for an isolated heatsink (heat dissipated through that little bit of copper under the chip) type deal.

[T3sl4co1l]

You're welcome to short them together (I'm sure it's recommended to do so), and you're welcome to flood around the pads with solid copper if you like (and for power dissipation, I do like).  But you should keep the soldermask as specified (SMD -- soldermask defined pads), or use thermal relief (NSMD -- non-SMD pads), so the solder joint (solder filling the gap, and the fillet / toe / whatever around the perimeter) stays good.

You may need to reduce the amount of solder paste applied underneath, to ensure it doesn't float up and break connectivity to the outer pads.  Or, specify non-tented vias of sufficient volume to [potentially] soak up the excess solder, which is a good idea if you need to dissipate a lot of heat.

Tim

[Falcon69]

Ya, that's what I've done Tim.  I was just wandering why they had done it that way, if there was a specific purpose to it.

Here's a pic of what I have done.  All those chips will look like this.  I simply just edited a new component part and placed a signal layer around the pads, didn't interfere with the preset part of the component for soldermask, etc.

[salbayeng]

It's my first post !

Part of the reasoning goes back to the old photo-plotter days, where you had to work with a fixed number of "apertures" , circles, squares , hexagons etc.
So each "pad" gets assigned an aperture on the relevant layers , copper, solder mask,  paste . Generally your PCB software will generate the apertures by scaling up a little (for solder mask) and down a little (paste=stencils) .   (remember one pin = one pad = one aperture)
So assuming you could make an odd shaped pad, then it's difficult for the mask and paste algorithms to figure out what shape to make, and even then if could make an odd aperture shape with concave vertices, that shape would snag when the blade of the stencilling machine ran past it. Finally if you sent a GTP gerber to a stencil maker, they would automatically put a little bridge across the odd shape, and break big pads into little panes.

You also need to put less solder in the central pads or the part will float up , so you need to manually tweak the area of the central pad.

The other big problem with asymettrical pads or paste apertures is they will make the part spin around during reflow. like this-> 

These multipad parts are a bit annoying though , as you need to make up special schematic symbols for each one.

[Falcon69]

Okay, that makes perfect sense, as for as the algorithms for figuring out the mask size, etc, within the software when the component was placed. However, for stenciling, tat also makes sense, except you can have stencils laser cut, which would allow for different shapes of pads.

But thank you for the explanation. Makes perfect sense when it is thought of that way. Never thought of it from a programming point of view for maske/paste dimensions that the software would generate for the offset.

[T3sl4co1l]

Yeah, a Gerber file is supposed to be, in essence, a flat, monochrome, dimensioned picture -- but its structure belies the method in which it was created.  Like PDF, SVG and other vector formats, you can infer things about the original source, beyond what the final shape would suggest.

Example: if you place an SMT component in the middle of a copper pour, not only do you get the fill of that pour (which itself might be constructed from lines or something), but a redundant pad is left in there, which lines up with the mask and (if applicable) paste openings.  PCB houses have software that detect these objects.  If you have something inconsistent (a pad object with no mask opening, or vice versa), they almost always flag it, just to check and be sure.

Tim

[salbayeng]

Yeah it's all sorts of fun when you try to make
(a) fiducials , they have a huge mask opening , but no stencil hole
(b) Logos ,  you can create multiple "colors" by patterning mask, copper, overlay (and even paste) in different combinations. Some of the time you are working with  a "negative" e.g. the mask.
(c) footprints with heatsinking fills attached to the pads.