multisim question

[xxngo]

Dear forum,

I was testing capacitors as voltage divider with dc voltage using 1uf and a 2uf all in series with 12Vdc .  Sure enough my measurments checks out, the smaller value cap gets more voltage drop on it.  but when i generate the same loop on multisim, i get 12V across the 1uf but nothing on the 2uf.  can anyone please tell me why?  I'm using multisim 10 and i'm pretty sure there's nothing wrong with the program, since most of the measurement i've done on it checks out fine when i breadboard 'em.

[3roomlab]

set simulation initial condition to zero and run (master setting)

[xxngo]

ohh thnx bro, I will try that....yah I realized that multisim sees the two caps as one, doesnt matter which position the cap is i can only get a reading across both of them no different than measuring directly at the source.

but yah thank you

[LvW]

Dear forum,
I was testing capacitors as voltage divider with dc voltage using 1uf and a 2uf all in series with 12Vdc .  Sure enough my measurments checks out, the smaller value cap gets more voltage drop on it.  but when i generate the same loop on multisim, i get 12V across the 1uf but nothing on the 2uf.  can anyone please tell me why?  I'm using multisim 10 and i'm pretty sure there's nothing wrong with the program, since most of the measurement i've done on it checks out fine when i breadboard 'em.

You cannot test (ideal) capacitive voltage dividers - neither in the lab nor with a simulator.
In practice, the voltages across the capacitors are determined by the parasitic parallel losses only!
That is the reason, each simulator requires that each node has a dc path to ground - and this is not the case BETWEEN both (ideal) capacitors.
Didn`t you get any error message?