My first PCB - MSP430 - Will it explode?

[Josh]

Edit: Thanks for all the comments - I've updated the design and it's in the post below for a second round of abusing =)

Okay, okay... I don't think it will explode, but this is my first PCB (and micro schematic really), so I was hoping some of you veterans could give me some feedback. If there's anything obvious I've messed up or done unconventionally, the constructive criticism would be much appreciated 

Some pictures are below and gerber and schematics are attached. The project is simple - it's just a MSP430 micro talking over USB with some digital IO. The board is going to be used to make a class compliant USB MIDI controller similar to the MIDI Fighter. I'm planning on using Seeed Studio's PCB service.

Some of my uncertainties are:
1) This is my first PCB so I don't really know if I'm doing it all right - did my research and passes design rule checking. But if anyone sees anything unusal or wrong that I did, I would much appriciate the learning experience gained from you pointing it out =).
2) This also goes for the schematic - first time with a TI micro and USB. Made with the DS on hand and checked with examples, but if somethings off I'd much appriciate the criticism =).
3) The USB pins are quite small and close together. To meet the solder mask -> pad clearance, I reduced the solder pad expansion from 0.1mm to 0.05mm on each pad. Is this the best option? My thoughts are if mfx is off, the mask could cover the pad and make it unusable. The other option is to un-mask the block of all 5 pins - but then will the pins become easily bridged when soldering.
4) The solder mask on the MSP430 has super thin gaps between pins. I can't imagine a strip this thin of mask will stick, but the footprint I download from TI - so it must work...? It also didn't cause any rule violations (I'm using the handy Seeed Studio template from here)

Any comments much appreciated by this newbie - thanks!





Gerber Files: https://www.dropbox.com/s/ksludp2c37k819e/PCB%20GERBER%20FILES.zip?dl=0

[Fred27]

Of the top of my head, SBWTDIO could do with a capacitor to ground. Some ESD protection on the USB data lines might be a good idea.

TI development boards are a good place to get some ideas on designs. Have a look at this one and see if you've missed anything: http://www.ti.com/tool/MSP-TS430RGC64USB

A great place to get MSP430 info is http://forum.43oh.com

Sent from my Nexus 6 using Tapatalk

[Josh]

Of the top of my head, SBWTDIO could do with a capacitor to ground. Some ESD protection on the USB data lines might be a good idea.

TI development boards are a good place to get some ideas on designs. Have a look at this one and see if you've missed anything: http://www.ti.com/tool/MSP-TS430RGC64USB

A great place to get MSP430 info is http://forum.43oh.com

Sent from my Nexus 6 using Tapatalk

Thank you! I wish I had that forum link before! It's a good one! Been looking at TI examples but didn't see that one yet - thanks.

A question - is the USB ESD chip more-or-less a necessity or simply just a "good idea"?

[alexanderbrevig]

Congratulations on taking the step to design your own PCB! It's a lot of fun

@Fred27 is giving you the best tip; research application notes and reference designs. You will thank yourself later.

More generally, here's my 2 bits (I'm new too);

• You're not doing power VCC right, which is made clear by:
  
• Your decopuling capacitors (C7..9) are not correctly laid out (see below)

The thing about power and decoupling capacitors is that it's not an exact science (well, it really is) so  the way you have it may very well work. Especially if you use a proper power supply while testing. I know by experience that it really sucks to find it does not work in the real world situation off the intended power supply.

Power should be supplied from a thicker trace (you got that right  ) but, the path must look like:
VCC -> CAPACITOR -> IC_VCC

Doing:
VCC -> IC_VCC -> CAPACITOR or CAPACITOR -> IC_VCC -> VCC is not right.

The capacitor must be close for it to function the way it is intended

[alexanderbrevig]

A question - is the USB ESD chip more-or-less a necessity or simply just a "good idea"?

Any time a user may come in contact with your circuitry (i.e the USB plug) ESD is a good idea. If you leave it out, chances are someone will destroy if after doing something odd like rubbing against a balloon. You can't control how they handle your circuit, only how you handle their input.

[chicken]

R2/R3 at 27K seem high. From memory those should be 27 ohms or so.

Another TI document to check out is the MSP430F5529 launchpad documentation, the USB bit is identical with your MCU.
http://www.ti.com/lit/ug/slau533c/slau533c.pdf

[Josh]

Thanks for the reply alexanderbrevig! Couple things:

1)

Power should be supplied from a thicker trace (you got that right  ) but, the path must look like:
VCC -> CAPACITOR -> IC_VCC

Doing:
VCC -> IC_VCC -> CAPACITOR or CAPACITOR -> IC_VCC -> VCC is not right.

I was reading this post where the top answer said this did not matter... thoughts?
Regardless, I'm going to update it as you say as a best practice thing.   

2)

The capacitor must be close for it to function the way it is intended

...but on that note, I suppose my caps may not be close enough to the pins. Yet the board is on 50 mm square, so they're not all that far?

3) Do your comments also apply to the load capacitors on the crystal. My understanding is that these are load caps required for the xtal to oscillate accurately, rather than byspass caps.

R2/R3 at 27K seem high. From memory those should be 27 ohms or so.

wow thank you, big error on my part! (edit: atleast I had the right ones in my DigiKey cart!)

[Tac Eht Xilef]

3) The USB pins are quite small and close together. To meet the solder mask -> pad clearance, I reduced the solder pad expansion from 0.1mm to 0.05mm on each pad. Is this the best option? My thoughts are if mfx is off, the mask could cover the pad and make it unusable. The other option is to un-mask the block of all 5 pins - but then will the pins become easily bridged when soldering.
4) The solder mask on the MSP430 has super thin gaps between pins. I can't imagine a strip this thin of mask will stick, but the footprint I download from TI - so it must work...? It also didn't cause any rule violations (I'm using the handy Seeed Studio template from here)

The decent prototype places will check and adjust the mast to suit their processes, although it's probably not a good idea to rely on it completely. I can say I've used iTead for boards with 0.5mm pitch packages (i.e. 0.2mm or so between pads) & the mask between pins has been OK on all bar the first occasion - and that may have been the fault of my footprint.

[codeboy2k]

Good first job!  I like the MSP430 too, more people should use it.   You don't see it too much, as most people choose a PIC or AVR.

I won't repeat what's already been said. 

Here's my additional thoughts on your board:

1) USB 2.0 needs 90-ohms nominal impedance, and on a two layer board this means you need wider traces. I've given some trace widths and spacings for 90-ohms on various thicknesses of 2 layer boards. Note that thinner boards can get away with narrower traces, so if you find that you just can't route a wide trace, you can choose a thinner board and use a narrower trace width.

FR4 Er = 4.2
1 Oz copper thickness = 1.4 mils

90 ohm nominal trace width/space for various 2-layer board thicknesses (in mils):
board thickness : 1.6 mm (63 mils)  50/6 or 55/8 mils
board thickness : 1.2 mm (47 mils)  40/6 or 42/8 mils
board thickness : 1.0 mm (39 mils)  34/6 or 36/8 mils

2) the termination resistors R2 and R3 should be 16-33 ohms, and placed as close to the CHIP as possible, near the DM and DP pins, not close to the USB connector. The two  filter caps C5 and C6 should also be close to the USB transciever, i.e. close to the micro's DM and DP pins.

So you need to come off the USB connector with the wide track widths above, and maintain that track spacing right to the termination resistors that you will put at the chip pins, just before entering the chip.

3) the 1.5k pullup should be on the D+ side before the termination resistor, NOT on the microcontroller's DP side.  Since the termination resistors and filter caps want to be close to the micro, they will take all the space up there, so keep the 1.5K near the connector and run a thin trace to it.  It's just a pull-up control, so not a problem if it's long and far from the micro. But the resistors need to be close (as well as the crystal.. see #5)

4) ESD protection diodes should be used too, and these should be placed close to the connector, on the D+ and D- lines and pull up to VBUS and down to GND.  A MAX3207 in SOT-23 or Semtech RCLAMP0503F in SC-70-5 would work (the Semtech is slightly cheaper, even though it has 1 more port).

5) The crystal and caps want to be close to the pads (doesn't everything!) so try to see if you can rotate the crystal 90 degrees and get the crystal closer and the caps in between.  If you can't do that then swap the traces at the microcontroller pins 45 and 46, and come off the top of C2 down to pin 45. This will at least put C1 and C2 in between the crystal and the microcontroller pins, but I would still try to re-orient the crystal and get  it and the caps closer to the micro.

You look like you are using all 1206 parts.  They are easy to solder by hand, but you might find them hard to get near the pins as you need them to be, especially things like decoupling caps and for the USB termination and filtering.  If you have routing issues with these bigger parts you should consider smaller parts, at least for these components. Smaller parts are not that hard to solder, and you don't have too many anyways.

Cheers!

[Neilm]

VCC -> CAPACITOR -> IC_VCC is needed so the capacitor filters the high frequency current pulses generated by IC from the supply and any other components on it. This becomes important when you are designing for EMC compliance, or have sensitive circuits on that rail.

You look like you are using all 1206 parts.  They are easy to solder by hand, but you might find them hard to get near the pins as you need them to be, especially things like decoupling caps and for the USB termination and filtering.

In addition, smaller components tend to have less parasitic effects which are important at higher speeds. You might find the following link useful for background reading. https://www.maximintegrated.com/en/app-notes/index.mvp/id/5663 I tend to not have too much trouble with 0603 packages and a good pair of tweezers.

Neil

[Josh]

Thank you all for the comments! It really helps, and I'm learning 

I've remade the board with the suggestions posted and I also changed the IO scheme (including adding some shift registers). My changes are posted below - let me know what you think!

board thickness : 1.6 mm (63 mils)  50/6 or 55/8 mils

I wasn't sure what 50/6 meant, but I increased the thickness to 0.4mm and followed this guide: http://www.cqpub.co.jp/dwm/article_english/dwm050/USB2_05.htm
What was difficult was that the pins on the connector and chip were opposite (ie. the traces have to swap sides) so I did an odd trace around the connector - I hope it's fine. Only other way is via's which I hear are bad for this. There's not enough space between the resistor pads to route the swap through there.

3) the 1.5k pullup should be on the D+ side before the termination resistor, NOT on the microcontroller's DP side.

I ended up keeping this after the termination resistor b/c it fit there anyway - and that's how the TI reference schematics are, so I'm thinking it's ok?

Thank you for all the help codeboy2k!


Here is the updated board:

Top+Bottom / Top Only / Bottom Only


USB+Power+MCU / Main IO / LED Matrix IO / Button Matrix IO

[Josh]

Good first job!  I like the MSP430 too, more people should use it.   You don't see it too much, as most people choose a PIC or AVR.

I'm quoting this because I'm not sure where your other post went? It seems to have disappeared... I did manage to read it all and make some changes though - so thank you (no it wasn't too long haha). Here's what I came up with based on your suggestions.

• I opted for 2 single ESD diode chips (Diodes Incorporated DRTR5V0U1SO-7) and changed the traces. I still had to fit that ground via in there, which adds a couple bends in the trace - which I could minimize by changing to a smaller via (can half the size of all vias to be at the min specified by the manufacturer, but then I may as well do all of them because they're all the same).
• I also changed the xtal for a smaller package with integrated caps - it was also cheaper, what a deal. I put a cutout in the gnd plane below the xtal per some recommendations to reduce any shunt capacitance (I read mixed opinions)
• I dropped the 33k resistor between the USB connector shield and ground per your comments, as it's nice to reduce the unique part count where we can
• I also added a cap on the SBWTDIO line based on what I read from other sites.

I do hope codeboy's post comes back... it was very helpful.

[codeboy2k]

That looks better now!   Yes what happened to my post? it was indeed very long but I'm glad you were able to see it and make some changes based on my suggestions.   I'm happy you saw it, that's all that matters. 

Yes, those 2 ESD diodes was exactly what I was thinking when I suggested it based on the wider traces now. 
USB overall looks way better -- better impedance, no stubs and minimal discontinuities 

I think you misunderstood me, I didn't say that you should remove the 33k resistor from shield to ground, in fact I suggested that you even add a second pad in case you wanted to put a small cap there parallel to the resistor.  There are many camps when it comes to connecting the shield to the digital ground -- some people like a direct connection, no resistor, some like a 1Meg resistor, some like a 33k, some like a 100k, some like a 1Meg resistor parallel to a 0.47u cap. My suggestion was to add cap parallel to the resistor, in case you found it was needed. You can put the pad, just don't populate it. I would not go into production without the option of at least putting a resistor there from shield to ground.  You can put a single pad, or two pads if you have room. and also have the option of just using a 0-ohm resistor too.

I've marked up the image a little bit

1) in the right corner, near the USB connector, I still recommend at least 1 pad there for a resistor, and another in parallel if you have room for a cap too. It's better to go to into production with the pads already there for a resistor or cap or both.  You can use a 0-ohm link, or just put a resistor there anyways.  There are many camps, as I said, but you should produce the board with the option available to put it there later if you need it.   If you don't want to populate it at all, you can make a custom 0603 pad that can be shorted with solder, like this one:



2) Are you hand-soldering the board, or getting it reflow soldered?  If you are reflowing the board, then the wide traces on the pads where I have circled might cause tombstoning. i.e. the pullup resistor, and the 2 termination resistors.  Tombstoning occurs when one pad has more thermal mass than the other pad -- one side flows first because it gets hotter first, but the other side is cooler and still not wetted to the part, and it lifts up and away.  See the youtube video at the bottom. Tombstoning is mostly a concern for smaller parts like 0201 or 0402, but it can also happen with 0603, and much less chance with 0805 parts.  So to prevent tombstoning you might want to neckdown just a little bit where the wide trace enters the top pad of R4, to make a smaller link between the wide trace and the pad, increasing the thermal resistance there. Also,  increase the trace width of the trace leaving the other pad of R4, to give the other pad more thermal mass. So make it thicker where you have the room.  Also, use an 0805 part for those resistors if you can find the space, ie for R1, R2 and R4.  You can also try to balance out the thermal masses on both pads of the R1, R2 resistors.  So where I circled at the termination resistors' connection to their caps, you can make that trace wider too, giving it more thermal mass and slowing it down during the reflow. Don't go too wide, otherwise the capacitors will have tombstoning problems next The point is to try to give both pads near equal thermal mass so that you minimize the chance of tombstoning.  (PS: Even if you are going to hand-solder only, I would still change the design to minimize tombstoning while your thinking about it now.  If you have the room for 2 or 3 slightly larger parts and can make a few small changes, then there is no good reason not to)

3) I like the new choice of crystal.  I always thought that other crystal was huge   I recommend you remove the ground trace I highlighted in yellow.  Leave the via to GND near the crystal.  At AVSS2 pin 44, use a via to GND on the inside of the part, i.e. move the two vias at the top of the part just down a little bit to make room, then put a via to GND for AVSS2 pin 44.  You want the GND connections to be short and lowest inductance, i.e. not over a long trace.

Cheers!

.

[codeboy2k]

one more I just noticed...

The connection from SW1 to pin 9 on U1 cuts across the bottom and divides your ground plane up there.  This is absolutely not going to be an issue, and you can leave it as it is if you want, since there are no signals on the top side in that region.  But I wanted to mention that you can elimate 2 vias and bring that trace to the top side if you go between pin 1 and pin 48 on U1,  similar to the USB pullup trace.

[Josh]

Thanks again for all the help - yeah it's odd the old post is gone.

Talking about the 33k resistor - I thought some argued that it could be done with so I did away with it - but I like your idea of the pad that can be shorted.

I'll be soldering by hand - will it still be advantageous to make the changes re: tomb-stoning you mentioned in this case? Nevermind, kept reading on and saw your suggestion. A thought, maybe necking is not for R4 because reducing the trace then going to a large pad would add an impedance change? Can make that one a 0805/1206 though. As a side note, I really don't expect to be reflow soldering this.

With the ground trace, I was a little confused, because other suggestions included making sure that power/ground traces around decoupling capacitors be routed to the cap first, then to ground or Vcc. In this case the caps are still there, but integrated into the crystal. So I was unsure if the same guidelines applied. I suppose the crystal caps are load caps instead of decoupling cap, maybe that's an important difference?

In regard to routing SW1 on the top: to bring a trace between the MCU pins, I have to shorten them ~0.2mm for clearance. The top trace is a more elegant solution - is it worth the slightly shorter pins? (I know, probably splitting hairs here)

Anyway, will have an updated board tomorrow to post up here!

[codeboy2k]

re:  33k shield resistor: Yes, it's good to put a pad there for shield to ground and then you have the choice to short it with solder or put a resistor, a cap, or a ferrite bead there if you find you need to.  What you eventually end up using is more often an environmental decision.  How will it be used? Will it be in a RF noisy environment that is coupling lots of noise into your system? Or is the device an RF generator that can radiate into the environment?  There are many situations.   Just make sure that the pad you place is an 0805 package pad, not 0603.  0805 is large enough to accommodate most things you might want to put there.

An ideal system shield is different and separated from the system ground, and the shield (as a system) is designed as a low impedance path to earth ground.  You want it separate, so that HV ESD spikes on your vcc and data lines are shunted into the shield and the metal case, and to earth ground, going around your device electronics.  But what if you don't have an earth ground, then what should you do?   This is where some say connect shield ground directly to system ground, and allow HV ESD and EMI to ride on your system ground.  This actually raises your device's system ground during the ESD event, but because the ESD event is a common mode event, it raises everything, so your device doesn't really care, everything keeps working, the spike is shunted to ground and dissipates on your ground plane.  This is very good, actually.  It's the same with any RFI conducted in, your ground just floats up and down with the conducted RF energy and your device just keeps working.   What you are trying to do with the SHIELD-GND connection is to get both HV ESD spikes and low voltage RFI that is coupled in via the voltage and data lines to be quickly shunted to (earth) ground with as low-impedance path as possible. I put "earth" in brackets because that is the ideal destination, but in systems that don't have an earth, then the system ground is the next best place to put it.  And this is also why some engineers like to use a parallel RC to connect the shield ground to system ground. The resistor provides a DC path for the shield to system ground, to keep these two grounds at about equal potential, and the capacitor shunts any conducted RF noise (RFI) to ground.

BTW: in this scenario, your ESD protection diodes should ideally be on the shield side, connected to shield ground and VUSB, not on the system ground side or VCC side

The downside of directly connecting the USB shield to your system ground is that it can cause the USB shield to become an antenna for any ground currents created by your device and riding on your device's ground plane.  This is mostly going to be a problem at higher speeds and with higher device currents, for example a big FPGA board.  At your lower speeds, and with your layout (see below, re: decoupling caps) you probably won't have much switching currents running on your ground plane that can get conducted into the USB shield anyways, so you can safely tie them together without worrying about it becoming an antenna.  However, even a single resistor here will help attenuate these ground currents if you do find that you have them in your final design.   

In my opinion, however, my best practice has been to assume that, in an ideal situation, the shield will be connected to Earth Ground at the PC HOST end (or at my own end if I have an earth ground), so I use a 1 Meg resistor and 0.47u capacitor in parallel at my DEVICE end.  This combination provides a low-impedance path for shunting high-frequency RF noise to ground and a DC path to keep the shield and ground at about the same DC potential.  Then make sure to do all the right things on the system ground planes to reduce high-frequency ground currents on my planes so the device does not become an RF transmitter.  If I can't reduce conducted EMI originating on my device, then I'll use a ferrite bead to connect the shield to ground, thus blocking any RF energy from reaching the shield.  This has the downside that an ESD event or conducted EMI into my device will cause it to fail with data errors since the system GND can't rise up with the common mode voltage.  The device needs to recover from the data errors at the upper protocol layers then, and if this is a frequent event (i.e. the environment it is operating in causes this to be a frequent event), then it can seriously degrade system performance.

Regarding your decoupling caps, they are placed well enough. The ground traces on the top are short and when the device needs current in a hurry it will source it via the cap, into the VCC pin and out via the GND pin back to to the cap and then reach the GND plane.  This is very good, since it keeps this HF switching off of the ground plane and keeps it all on the top traces only.  The goal here is to reduce the size of this loop, which will reduce EMI and ground bounce due to trace inductance. That's why you often see decoupling caps loaded on the bottom side of PCB's, since it makes the smallest possible loop for these HF switching currents. In your case I think you'll be OK with what you have, and you won't need to do anything on the bottom (so you can keep your bottom side free of parts).

Yes, the crystal caps are load caps, not decoupling.  They can go to ground directly.  The other trace should be removed and connect the ground pin directly to the ground plane.

re: SW1, shortening the two pins by 0.2 mm to make some room for routing a trace won't cause any issues, because you are using a gull-wing package, so the solder is mostly at the outside ends of the pad and there's enough pad left to make it work. I would not recommend it for a QFN package (no leads). 

[Josh]

Made a bunch of changes then saw you're message ...  Anyway, here's what I've got now. I opted to keep the 0603 resistors and just change the trace thickness for tombstone prevention as I'll just be hand soldering and the larger components make the fit quite tight. Given what you've said I think this will be an ok compromise, the info is very good though.

I added the DNP resistor and cap for the USB Shield and made a custom footprint to aid in shorting the resistor's pad. I had to make it slightly different than the one you posted because of seeed's required clearances. I also needed to omit the solder mask for the whole space between the pads - hope that's ok, and certainly not an issue for now while shorting. You mentioned putting an 0805 pad for flexibility - before I read your post I put 0603 package pads so that's what's on there right now.

Another thought about the SW1 trace splitting the ground plane: the IO headers on the left side are analog - so should the ground plane be split up even more than it is? Precision really isn't an issue and they will be fed by pots (ie. extremely slow changing analog signals), but I've read recommendations to split the ground plane for analog signals to isolate and HF currents on the analog ground plane from the digital system ground plane.

(also Altiums 3D is pretty fun. The model's aren't necessarily accurate here though)

edit: as a note there are also some components on the bottom already (shift register and some caps and resistors), but wanted to keep it as empty as possible to avoid splitting the ground plane and to make routing easier during that phase.

[Josh]

re: SW1, shortening the two pins by 0.2 mm to make some room for routing a trace won't cause any issues, because you are using a gull-wing package, so the solder is mostly at the outside ends of the pad and there's enough pad left to make it work. I would not recommend it for a QFN package (no leads).

moved the switch trace to the top...

[codeboy2k]

"moved the switch trace to the top..."

Good. Because that helps with my next suggestion:

Regarding splitting the ground plane too much.. your JTAG signals SBWTDIO and SBWTCLK cross a split made by VCC, which might not be an issue since JTAG is only used during debug/programming and it's not that fast anyways (I've seen MSP430 programmers up to 4 Mbps on the clock), so I was thinking you could probably get away with leaving that split in... then I started looking at the big split under the IC, made by the 3.3V power, and saw that DVSS1 and DVSS2 are below the split.  So with the SW1 trace on top now you can also reroute the 3.3V power to not cause the split under the chip like that.   So in my attached image you can perhaps remove the red parts and re-route via the yellow traces.

What size cap did you decide to put on SBWTDIO ?  1 nf is a good compromise for reset and high-speed programming.

The analog section doesn't need it's own ground plane. It's fine just as it is, and your analog parts (the pots) are low bandwidth anyways.  Your pots should have low-pass filtering either in hardware or  in software, otherwise you will get noisy and erratic behaviour.

It's looking good. 

[codeboy2k]

Re: C11 and AVCC pin 7

Normally I'd want to run that power trace straight back to the regulator output so that it's not sharing any current with anything else.   If you can do it that way, then great!  However, I think in your case it's less important since you are only using the ADC's for reading potentiometers, so it's less critical for you. Also your onboard voltage reference has some PSRR which will help keep AVCC noise out of your ADC samples.  I'll think you'll be fine with that AVCC trace sharing with the DVCC back to the regulator.

[Josh]

Good. Because that helps with my next suggestion:

Good call on re-routing the power trace! 1nF sounds good - would have been nice to not add an extra item to the BOM but the next lowest cap under TI's 2.2nF limit I have is all the way down at 10pF, which I imagine will do nothing for the line. Looking close to prototype ready I think! Thanks again for all your help on this - really appreciate it.

[alexanderbrevig]

This thread is amazing You're a fast learner Josh, and codeboy has plenty of good advice! I've learned a lot from this too.

If I were you Josh, I'd align your headers on a 100mil grid so it's easy to use strip-/vero board for prototyping and snap in on top. This may just be something I like because I'm used to it but it's worth considering maybe?

[Josh]

This thread is amazing You're a fast learner Josh, and codeboy has plenty of good advice! I've learned a lot from this too.

If I were you Josh, I'd align your headers on a 100mil grid so it's easy to use strip-/vero board for prototyping and snap in on top. This may just be something I like because I'm used to it but it's worth considering maybe?

Thanks alexander! Good idea - putting the headers on a grid so they align with a board. I'm planning on soldering directly to the board for the projects I'll be making with this (ie. no headers except for programming). I haven't decided, but may still rework it with 100mil spacing for flexibility.

Here's a quick mockup of a simple first application I'm going to use this board for. It's a Midi Fighter copycat 16-button midi controller.

[codeboy2k]

Based on the new layout I only have  a few more suggestions then I think you can get it made.

1) I still don't like the VCC rail cutting across about 20-21 digital lines on the right.. I think these are not going to be high-speed digital I/O anyways, so maybe it's not really an issue, but perhaps it can still be improved there.  Also in the same place there is a 5V VUSB rail cutting across a few signals that we can fix..

2) the JTAG lines cut across a gap in ground too, This is really not  big deal, but these gaps cause EMI due to the return currents having to find a path around the gap, and the EMI can couple back into your system and give you trouble during programming.  The trouble can be enough to cause your JTAG to only work at 400KHz instead of 4MHz, In this case, JTAG is not a big deal since it's only used in test and development, but once again if there is an improved layout available, why not try to do it right?

So, in my image below, I make some suggestions you can try to see if you can improve these areas.  After this, I think it's good to go !

a) GREEN CIRCLE: C3 and C14 circled in blue, move them to directly under U1 and connect them to their U1 pads and the ground plane
b) GREEN TRACE: the trace in green is VUSB can be removed and go straight up to the 5V header pin, I think there's room on the top side (DARK GREEN TRACE)
c) YELLOW: the same 5V/3.3V/GND header and the JTAG header can swap positions, and then you can eliminate the SBWTDIO and SBWTCK lines crossing the VCC trace, circled in ORANGE. When you re-route these JTAG lines there is plenty of room so use it up, keeping the lines away from the crystal to prevent crosstalk.
d) CYAN: the VCC trace that cuts across 20 traces or so from C16 to R5 can be removed and try to follow the path in dotted CYAN instead. basically it's cutting from the AVCC decoupling cap under that trace and pin, then follows edge of U1 pins along the bottom and right sides, and up and out the top right corner, following under the trace for the pullup resistor control, to get to the voltage regulator.  This actually feeds power to AVCC first, then the digital sections.   The new trace has a stub at U1 pin 28 that connects out to the via for C9.   Leave the via and everything else where it is so that the decoupling loop is on the top layer.

That last step actually does split the ground plane a little, but it's a good split I think.  It ends up splitting the chip across analog and digital sides, but that is unintentional.  I think it's going to be a better split then you had before though.  I'm not usually one to split the analog and digital grounds unless I need to meet a very specific noise spec, then I'll start intentionally putting gaps in the ground to direct ground currents out of my analog section... but this isn't really the intent here.  It just seems like the VCC is better placed there rather than breaking up the IO lines.

Give it a try next and let's see what it looks like.  After this, I think it's good to go.

[codeboy2k]

This thread is amazing You're a fast learner Josh, and codeboy has plenty of good advice! I've learned a lot from this too.

If I were you Josh, I'd align your headers on a 100mil grid so it's easy to use strip-/vero board for prototyping and snap in on top. This may just be something I like because I'm used to it but it's worth considering maybe?

Thanks alexander! Good idea - putting the headers on a grid so they align with a board. I'm planning on soldering directly to the board for the projects I'll be making with this (ie. no headers except for programming). I haven't decided, but may still rework it with 100mil spacing for flexibility.

Here's a quick mockup of a simple first application I'm going to use this board for. It's a Midi Fighter copycat 16-button midi controller.

Yes, thanks too, Alexander!  And you're very welcome, Josh, I'm happy to help! 

That's a good looking 3D mockup, what software did you use to make that?  I had a MIDI keyboard when I was younger but not any more.   This 16-key assignable pad can be useful