N stage parameterised flip flop synchroniser for 8 bit input.

[AnuI]

Hi all,

I want to design an N stage flip flop synchronizer.

For one bit input, I can use shift register of N bits and have my parameterized synchronizer  as shown in code.

//////////////////////////////////////////////////////////////
module N_stage_synchronizer #(
  parameter NUM_STAGES = 2
) (
  output    sync_out,
  input     async_in,
  input     clk
);
 
  reg   [NUM_STAGES:1]    shift_reg;
 
  always @ (posedge clk) begin
    shift_reg <= {shift_reg[NUM_STAGES-1:1], async_in};
  end
 
  assign sync_out = shift_reg[NUM_STAGES];
 
endmodule
/////////////////////////////////////////////////////////



But what to do if the input is a vector.
For eg: Async is 8 bit.

Then how to do it?
Do i need to use an array?

Any help would be appreciated.

Thanks.