Author Topic: Need Guidance in Current Limiting Variable Design Technique...  (Read 795 times)

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Offline techguru

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Need Guidance in Current Limiting Variable Design Technique...
« on: November 25, 2017, 05:04:34 am »
Here is the circuit i am working,

                                           Now i want adjust the current limiting resistor to adjust my current but the problem i cannot have variable resistance of 0.3 ohm(potentiometer). how to implement the resistor to adjust the current ? help me in this regard..
 

Offline hugo

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #1 on: November 25, 2017, 06:05:11 am »
Hi,

- U1 needs power.
- You need to add a potentiometer at the U1 non inverting input.
- Varying the voltage at the U1 non inverting input then changes the load current.
 

Offline David Hess

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #2 on: November 25, 2017, 03:22:41 pm »
That configuration is usually used for a rough maximum current limit but it can be modified.

Add a resistor in series with the emitter of the current sense transistor and then draw a calibrated current from the emitter to ground to create a voltage across the resistor which lowers the voltage necessary across the current sense resistor to trigger the current limit.

This is also how foldback current limiting is sometimes implemented so do a search for that to get examples and ideas.

 
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Offline danadak

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Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 
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Offline techguru

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #4 on: November 26, 2017, 05:38:39 am »
Dear Hess,

              Foldback current limiting ment to give protection to series pass transistor. It also increases dropout voltage...Could any body can give exact solution for my circuit?
 

Offline David Hess

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #5 on: November 26, 2017, 10:19:47 am »
Foldback current limiting ment to give protection to series pass transistor. It also increases dropout voltage...Could any body can give exact solution for my circuit?

Foldback current limiting has nothing to do with dropout voltage.  It lowers the current limit as the output voltage falls but it can do it in the same way which is why I used it as an example.

The example below shows the idea using LM317 regulators.  The current drawn through the second resistor creates a reference voltage which follows the output voltage and subtracts from the regulator reference voltage to turn it on earlier lowering the current limit.  I could not find any examples using bipolar Vbe current limit circuits because they are so soft that it is not commonly done.  Usually a differential pair is used instead.

Update: I found an example in the Tektronix 5111A power supply shown below.  Resistor R826 lowers the Vbe current limit by creating a voltage across R827 which adds to the voltage across sense resistor R815.  In this particular case using a resistor increases the current limit as the output voltage drops which is the opposite of foldback current limiting; I am not sure why Tektronix bothered to do this here.  If you want the output current to be constant, then R826 should be replaced with a current sink as described above.

« Last Edit: November 26, 2017, 10:40:54 am by David Hess »
 
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Offline techguru

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #6 on: November 27, 2017, 01:39:42 am »
Could any body help in current control Circuit for this attachment. how to adjust current for this circuit.
 

Online Ian.M

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #7 on: November 27, 2017, 03:30:37 am »
From the general style of the schematic shown, it seems likely that you are using LTspice.   There are many LTspice users here, so you are far more likely to get help if you attach the sim (.asc file) so others can run it.  If it uses your own or 3rd party, models or symbols, zip them up with the .asc file so we can be certain we are running the same sim.

With that out of the way, the usual way of implementing adjustable current limiting in a constant voltge PSU is to have two feedback loops, one for voltage and the other for current with an arragement so that the one demanding the lowest output has control.   Classically one would use two differential amplifiers (e.g. long tailed pair) or OPAMPs, one comparing the setpoint voltage to the output voltage, and the other subtracting the voltage drop across a current sense resistor from a bias signal representing the desired output current, then have a pair of diodes and a pullup resistor so either could pull down the pass transistor drive signal and the lowest has control.  The devil of course is in the details - as the feedback toop that doesn't have control is effectively open so tends to drive to its upper limit, which means that, due to the loop amplifier's limited slew rate, it takes time to recover, so when rapidly transitioning between CV and CC modes, it briefly overshoots the new limit.   This can be mitigated by arranging for the inactive loop to stay closed, but with a fake feedback signal that keeps its output near but above the active loop output to minimise the timke it takes to regain control.  Also with  OPAMPs and other high gain amplifiers in the loop, phase shift round the loop means stability is a serious problem and without compensation it will be likely to oscillate.   You need to do the loop analysis properly as mis-applied or over-compensation may make the situation worse, especially if you change the load, or seriously degrade the system's response to input ripple or rapid load changes.

For this reason hacks like a base pulldown transistor, roughly sensing the current through the pass transistor's emitter resistor are popular because they are fast enough and have low enough gain to avoid most of the stability problems.    Back in reply #2, David Hess suggested how you could add an emitter resistor for Q3 and a current source (actually a sink) between Q3 emitter and the 0V rail to adjust its setpoint.   Assuming it currently limits at 2.0A, a 0.3R resistor and a 1.5A current sink would adjust the limit down to 500mA.  This is obviously impractical, but if you increase the new emitter resistor to 60R, it would only take 10mA to reduce the limit down to 0A, so an adjustable 0 to 10mA current source would give you full control.  In practice the existing circuit wont limit at exactly 2A so the extremes of the current control range may have a dead zone or it may not actually reach the limit, so it will need a bit of tweaking to get good reliable results.  Also due to the limited loop gain, the current limit will be rather 'mushy' - that's the price you pay for a circuit that is so simple and inherently stable.
 

Offline techguru

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #8 on: November 27, 2017, 04:34:39 am »
Dear Ian,

            I could get the connecting a emitter resistor with Current sense transistor Technique. I have also attached the LTspice file with this reply. Thanks Ian.
 

Online Ian.M

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #9 on: November 27, 2017, 05:25:43 am »
Well that schematic is incomplete - as has been pointed out earlier the OPAMP needs power supplies and you've got to provide a source for the 15V rail, but I've added the emitter resistor and current source as David proposed, and I detailed.  HTH
 
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Offline techguru

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #10 on: November 29, 2017, 04:10:43 am »
Hi to all,

             Today i went through Mr.Lorton Psu design. I have attached his design. You all can give your comments for current limitation loop and stability of the circuit. Thank you..
« Last Edit: December 01, 2017, 12:10:50 pm by techguru »
 

Offline techguru

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #11 on: December 03, 2017, 01:32:24 am »
Whether this circuit can be used to construct voltage and current control circuit? Or any corrections has to be made? Please help ...

     Other thing is there is voltage divider driving transistor 2n2222 from current control operational amplifier. Why there should be voltage divider? What will be the voltage on that operational amplifier? Why?
 

Offline rstofer

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Re: Need Guidance in Current Limiting Variable Design Technique...
« Reply #12 on: December 03, 2017, 06:24:35 am »
You can see from the output transistors that you need to pull the base of Q1 down to get any output.  That means that both 2N2222s need to be conducting.  Therefore, you can figure that the base of Q3 is about 0.7V and the transistor is in saturation so the collector is about 0.3V.  Therefore, the emitter of Q4 is about 0.3V and the base of Q4 is about 1.0V.

The non-inverting input can only be adjusted over a range of about 0V to 5V (set by ZD1).  If the power supply output voltage is to be higher than 5V then there needs to be a voltage divider between the output voltage and the op amp inverting input.  The designer chose to divide the output voltage by 3 to get the divided output voltage in range for the op amp.

All numbers are approximate...
 
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