Tim are you sure about that? Usually the higher the frequency the easier it is to attenuate.
My classic example:
- I designed a 5kW high frequency inverter module. Multilayer board, "minimized inductance". It was built with ISOTOP / SOT-227 power modules, and I estimate it had around 15nH loop inductance. For something about as wide across as your hand, that's not bad at all.
- It rang like a motherfucker, 80% overshoot. Now, when you're starting with 650V DC link... that's a bit of a problem. We had to buy 1200V transistors just to do initial testing.
- Ok, so, it's multilayer, we've got connections to the opposite supply rail nearby. Let's try putting some clamp diodes in there.
8A diodes: toasted.
12A diodes: toasted.
30A diodes: survived. But the overshoot is still over 10%, and even being generous with stray inductance on the diodes and connections, that's over 40V applied across the die itself. In just a few nanoseconds.
By the way, the diodes failed mysteriously, barely warm at all. I suspect electromigration, but I really haven't heard anything concrete about high current failure modes. (Hot-spotting is unlikely because forward drop is resistive and PTC at those currents. Maybe there's something spooky like nonuniform forward recovery -- who knows, manufacturers are very quiet indeed about this phenomenon.)
- Later rev, I explicitly added about 100nH of stray to the layout.
Instead of ringing at 60MHz, peaking over 100A, and pounding the ever-loving shit out of the clamp diodes, this brought it down to a manageable 10MHz, the worst case overshoot to 10%, and the peak current down to 20A.
What's more, a proper RCD clamp snubber handled the energy cleanly, dissipating it (of which there is slightly more at high loads, due to the E = 0.5 L I^2 stored in the supply inductance) dissipated safely in a moderately sized resistor (there was under 400W total dissipation under worst case operation -- always over 90% efficiency for a 5kW high frequency module). At full rated output, the snubber power was a small fraction of losses, so this is a perfectly reasonable sacrifice.
- The moral of the story is, it's not even a sacrifice. Your inverter necessarily has junction capacitance and loop inductance. The only reason you're suggested to minimize inductance is because, if and only if you can get the resonant frequency higher than the switching speed, or the impedance sqrt(Lstray/Cj) low enough, then it won't be stimulated by the transients. In reality, especially with switching speeds so fast now, that this is neither possible nor reasonable, one must match the impedance to the circuit (roughly, switch Vpk / Ipk = Zo), and assign a reasonable frequency for the loop (usually, f_o > 20*f_sw is reasonable without incurring too much losses, while still being reasonable to deal with).
Tim