my noob journey to lower DMM noise (keithley mods)

[3roomlab]

this is interesting, the AZERO = OFF seem to permanently shave off a layer of noise. small, but it is removed. (last 3 log entry vs no. 242/243)
while in specifications AZERO is suppose to improve reading accuracy by 2ppm, it also seem to increase the internal p-p noise.

Before more shielding is tested, don't forget the bias / leakage current. This is the first thing to be fixed. The changed OPs are a real improvement only if bias currents are stay small.

i had a short check on this, it seem after the AGND shortening, the AC measuring of "signal" coming out of input socket is increased to about 650mV 
i will grab some time to meddle in this area. it is likely due to a capacitor i added to the zero buffer, maybe 
a short check on ohms show that AGND shortening also turned back the zero reading more towards "zero", as initially, AGND shorting was only applied mostly to integrator side

moar experiments to follow ! thanks again kleinstein
(i wanted to use lower no of samples, but i think the higher samples capture alot of crap p-p noise, and it tell something inside is still noisy, when i started i used to see only STDEV, but that is averaged and does not tell instantaneous 1 of p-p problems, esp popcorn. then i added KURT/SKEW, so that it tells how "flat" is the noise, which STDEV also does not tell. i think DMM noise thread should use KURT/SKEW)

[dr.diesel]

Wow your ambient temps are warm!

I'll repeat some of my tests with AZERO off, for comparison.

(Will have to be tomorrow night as the instrument is currently powered off)

[dr.diesel]

Kinda doesn't surprise me to see a slight difference with AZERO off.  To measure the zero offset you'd have to disconnect or float the input, measure, re-attach, math, for each read cycle right?

Wonder if Keithley has a paper on how that's accomplished?

[Smokey]

This is sure a lot of posts about how to make a Top Tier manufacturer, current model, $4630 USD list price, meter "Better".

[retrolefty]

This is sure a lot of posts about how to make a Top Tier manufacturer, current model, $4630 USD list price, meter "Better".

 Well this a well know watering hole for volt-nuts, is it not?

[3roomlab]

@ smokey ,  well i am still learning. thanks for everyones tips n nice technical threads that i can learn from. n of cos EEVblog for putting up with my immense nonsense  and splatters of rather noisy pic / plots.

@ retrolefty, i cannot be classified as voltnut (and i have no qualification to be 1 anyway), the best VREF i have outside of a DMM is a voltagestandard from doug (not that it isnt good enough). i think voltnutters may need a diff certification standard to certify voltnut-ness, maybe to DIY a VREF of verifiable 1ppm nut-ness  . and to top it off, this K2015 is uncalibrated, i do not have the ability to define a volt accurately beyond 10mV (in my own opinion).

@ dr.diesel, i read in keithley pdf, azero on will make MCU measure VREF n zero when it is sampling input. i read that some suggests to improve sampling, instead of azero always on, they program it to cycle on/off once every minute. im not sure if newer keithley gear does it in per sample basis, the pdf seem to indicate the K2015/2000 does it on per reading/sample (i cant remember which pdf it was).

and to continue with some "fault" finding, i re-measured the floating "noise". (for ref, VR 115 and VR116 is swap around on my PCB, with pin 1 VR115 connected to source, not VR116 p2 to source). trace is for pin1 VR115 (which is tied to opamp input), vert is 250mV/div, horiz is 2ms.div (i beliv i made a mistake "zeroing" my scope previously and got the units all wrong lol). the huge signal is with uni-t plugged into inputs, however, w/o anything plugged in, the noise is very low pic-161054 (vert 50mv/div). shorting plug, noise is undecipherable on scope. i think the jagged noise has something to do with my neighbor's new air-conditioner installed today

my theory of this noise, is it could be the higher input impedance of new opamps. i derive this hint from trying to measure a 9v battery, after removing the input, the voltage take 10seconds to reach 1.5v, and is still trying to dissipate. hmmmm ... with the DMM powered off, pin 1 VR115 actually only have 116ohms to AGND (input low). i wonder, did the JFET have a switched sampling and forgot to on its discharge? or it doesnt work that way ?

next i try something, i tie a 1M R across U107 to AGND. this results in the next reduced trace pic-163734 (250mV/div).by doing this, it also destroys the DC accuracy  .

next trace of +15 rail regulated noise, which i suspect the VREG did not fully regulate the input raw. causing the peak section to bypass more noise. 
i think i should try to solve the DC rail first. maybe a PMOS/NMOS low drop stage instead of a LM29xx.

so... it seems i did not really solve the noise at all from that last AGND tie up *sigh*, i must have miss-read the noise with the input open.

as consolation to myself, i add this gif chart. some logs before i stop logging to do the above rummaging in the innards. note the log in bottom half with azero off, esp 1NPLCx50repeating-average. it seems it is quite capable of maintaining a very consistent /predictable error rate, which seems like a good thing in long term logging? yes? esp note logs which exhibit low KURT/SKEW = a flat-ish plot

[Kleinstein]

This multimeter has a very high impedance imput, so for the 0.1 , 1 and 10 V ranges it is normal to have a rather poor defined response when open circuit. It is allready rather fast for the voltage going down from 9V to 1,5 V in only 10 s. In some sense this is good, as it indicates no excessive bias current but could also mean to low an input resistance. It is not unusual and nothing bad for an open input to slowly drifting all the way to its upper or lower limit. Watching this with a defined capacitor (e.g. 1 or 10 nF low leakage) at the input is one way to check for Bias currents.

The input resitance is specified to be very large (e.g. more than 10 GOhm), but usually is much higher (could be in the Tohms range). The other, usually more important parameter for the input is the bias current. Even if this should be in the 10s of pA range this does matter, as 10 pA flowing trough1 Mohm is allready 10 µV.

It looks like there is still some offset / bias errors to fix before looking for the noise. So far most of the noise is acouted for. So I won't expect significant improvements from shields or changes in the supply part. With now 3 noise sources of similar size that make up most of the noise, it is difficlult to get much better. Noise is allready something like 3 times lower than in the original configuration but this only helps if there is no excessive offset and bias currents.

There is also the possibility to have current noise at the input, so a test with something like 1 M resistor at the imput is importsant - there is absolutely for more of the same short circuit noise data.

[3roomlab]

ok so due to high impedance, the slow release of 9v measure is normal.

i jammed my uni-t at input in uA range AC, i could read an approx of about 0.07uA - 0.08uA. switching to 2W ohm, the uni-t itself have a impedance of 1kohm when measuring uA. and uni-t measures 101.06uA for the 2W mode (which i know is right on)
on capacitor mode, the uni-t sees the low range DC input as approx 330p. and hi range as approx 60p.
uni-t in AC mV mode, this time i can read the K2015 DC low range as 170mV, and high mode at 210mV approx. (looks like this property has changed). during 0.1v logging, the AC reading fluctuates to approx 165mV

in DC uA, there is nothing measureable by uni-t (K2015 in mV range)

edit : so i think it could just be be the VREG problem

edit ** i also took some time to retest some logs with the zero buffer. i removed 4 extra caps in the buffer section to see its effects. because i thought it affect the speed of decay in DC measure. without the need to post logs, generally its some increase in noise as usual, STDEV exceeds 140nV, and pp exceeds 1.1uV.

[Kleinstein]

Without knowing the input impedance of the Uni-t meter, the voltage readings have no real meaning. Also the Uni-t meter will have there own bias / noise.  So I won't use a second meter, except if you have a good pA - meter. The way to measure input bias is either a capacitor (and measure voltage over time) or a large resistor (e.g. 1 M or 10 M) and than use the Keitlhly meter to read. Both types of measurement measure slightly different things - so both ways may be needed to get a full picture. 

In case the uni-t has 10 M input resistance, 170 mV of DC offset would mean something line 17 nA of bias -- this is about 1000 times to much.

[3roomlab]

not DC, that is AC 170mV

in DC uA, the uni-t could not read anything (0.00uA). input impedance in uni-t uA is 1k ohm

**edit well silly me, there is some oddity with the uni-t mV range. and now by accidently using V range. i could actually use the K2015 to measure itself. the K2015 measures the uni-t with approx 10.08M impedance, with that, the K2015 measures itself with a bias voltage of 0.6-0.7mV (approx 1NPLC) which = approx 65pA. did i derive this correctly ? (this is assuming uni-t have no bias to affect reading)
oh my goodness, that took me a long time to get at

[Kleinstein]

The calculation is correct: 0.7 mV gives 70 pA of bias. This is not really bad, but also not as good as these meters used to be.  I remeber a typical number of 30 pA for some HP meters.
This could be due the the extra current from the LTC2057 or changed JFETs. Also the Optocoupler U107 can contribute a little.

There  a three types of bias:
1) leakage on the board, and chip cases - here guard rings and a clean board should keep this small, but some rest remains
2) semiconductor leakage (e.g. JFETs) - this part is temperature dependent, so keep the FETs cool
3) charge injektion from the AZ OP and the JFETs switiching for AZero.

The semiconductor leakage could be identified by changing the temperature of individual FETs. E.g. make the hotter or colder for soemthing like 10 K - this will about double or half that contribution.

Charge injektion from the JFETs should change with measurement speed, and essentially vanish if AZ is not used. So this is very easy to separate from the other parts.

Charge injektion from the LTC2057 should be a rather constant contribution. So there is a chance to compensate / trimm this to zero if needed. This would need a high value (e.g. > 100 M) resistor and a trimmer at the supply of the LTC2057.

[3roomlab]

i had another look at LTC2057, but there is no offset compensate pin. how do i accomplish this trim? (tried my luck at googling, but i dont think i understand what i should be looking for ). (*edit 100M + trimmer from output to -ve?)

edit** i have added some python code which cycles AZERO every 100 readings or so. this will be interesting logs to see from here

[Kleinstein]

There is no bias current trimming at OPs - at least I know of no OP that has this feature. However the special circuit used here with the other OP (now OPA2140 I guess) makes it possible to add a current. The supply für the LTC2057 is something like +-6 V relative to the input signal. It is relatively easy to use 2 resistors and a trimmer to get a voltage of something like +-10 mV relative to the output of the OPA2140. Then just have a high value resistor to make a small current in the +-100 pA range. The resistor will not decrease the input impedance by much, as its following the input on both sides.
However this would be only a last resort, to compensate the bias.

 Its not just the LTC2057 that contributes (typical 30 pA). Also the OPA2140 will give a little current (likely not more than the original AD822) and the JFETs also can give some current, both as gate leakage and drain-source leakage for those that are off. Also the autozero step may add current by charge injection - this part depends on the NPLC setting: so measure the bias at 1 NPLC and a high NPLC and without autozero (should be independent on NPLC in this case).

The bias from the LTC2057 (and injection from the AZ phase) is special in that it is mainly temperature independent so it can be compensated. With the Gate leakage for the JFETs this is not that easy, as the leakage strongly depends on temperature. So compensation with the extra circuit should only be used for the fixed part.

The first thing would be identfying the sources, e.g. by cooling or heating the candidates for bias one at a time.

[dr.diesel]

edit** i have added some python code which cycles AZERO every 100 readings or so. this will be interesting logs to see from here

In the simplest of comparisons, I ran a set back to back, one with auto zero on, one off and averaged the SD:

AZERO on = 0.397uV
AZERO off = 0.503uV

[Alex Nikitin]

I have just finished repairing my two Keithley 2015 and opened a new thread about it.
Cheers

Alex

[3roomlab]

@ alex ... nice ! another LTC2057 mod !
@ dr.diesel ... it seems your AZERO is doing well. mine is a bit noisy

as an interesting note since playing around with AZERO. in the case of K2015, a AZERO cycle in a sample seem to add approx 20-60ms extra latency.

**edit, now that my K2015 have become a frankenstein. how do i characterize it properly? hmmm (but then again, there is still the uncertain input current + Q120/Q105)
(i might be using the word characterize wrongly)

[Kleinstein]

To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:
1) with an external pA meter, peferrably battery powered
    -> no need for high accuracy, just about 1 pA resolution over a +-200 pA range would be enough
2) having a good short time stable voltage source and a high resistor (e.g. 100 M or 1 G):
   measure the volatage directly and with the series resistor. The differece comes from input current.
   Well setteld batteries might be good enough as a low noise source (e.g. 0 , +-3 V , +-9 V)

For a < 200 pA spec, the 65 pA measured so far does not seem to be so bad. Maybe one has to live with that. Still have to check the current at about +-10 V - it is likely higher there. At least this should not be from the LTC2057 - it's current should be independent from the voltage.

[3roomlab]

im not sure if i understand correctly, but is this correct? (with the LMC662 representing the picoamp circuit described here https://www.eevblog.com/forum/projects/picoammeter-design/)

  polystyrene cap MOQ 10pc, each $2 ... o my !. i guess i cant have polystyrene

[Alex Nikitin]

To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:

There is always a third way  . Log the voltage at 10V range, NPLC1, and discharge a charged to 10-11V polypropylene capacitor, say, 10nF, first time from +10V, second time from -10V. You need two runs as you don't know where/if  the leakage current polarity changes. The speed of the voltage change is essentially the leakage current (i=C*dU/dt, for 10nF and 10pA = 1mV/s).

Cheers

Alex

[Vgkid]

In my Solartron 7065 manual it suggest putting the meter in he lowest range. Placing a 1meg resistor across the input and reading the resulting reading. It actually gives you picoamp input bias.

[Alex Nikitin]

In my Solartron 7065 manual it suggest putting the meter in he lowest range. Placing a 1meg resistor across the input and reading the resulting reading. It actually gives you picoamp input bias.

Yes, however that would be the input current value only for one point in the range, close to 0V. The current changes (and in case of Keithley 2000/2015 - considerably so) over the input range from -10V to +10V. Discharging a capacitor would give a reasonably accurate result, taking into account the input capacitance of the meter (it is in my estimate is less than 1nF, which would give an acceptable 10% error for 10nF capacitor) .

Cheers

Alex

[Vgkid]

^^^ Thanks.
 Im looking forward to selling that machine. I learned a ton about multimeters by poyring over its manual, and fixing it. Using tyat method to meazure the input current. Initially it gave 120-140pA. I cleaned it droppex to 60pA, resoldered the connections to the input relay 17pA. SUCCESS
then that rose to 40pA, i gave up.

[3roomlab]

To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:

There is always a third way  . Log the voltage at 10V range, NPLC1, and discharge a charged to 10-11V polypropylene capacitor, say, 10nF, first time from +10V, second time from -10V. You need two runs as you don't know where/if  the leakage current polarity changes. The speed of the voltage change is essentially the leakage current (i=C*dU/dt, for 10nF and 10pA = 1mV/s).

Cheers

Alex

great idea, discharging 68nF in progress
i discharged from 7.4564v to 6.7629v in 20s. if using the equation, it gives 34.7mV/s. how do i compensate for charge voltage or the 68nF?

**edit round 2, charge @ 7.4558v, 200s, left charge @ 3.4587v, 20mV/s
round3 1.3671v discharged in 50s, 27mV/s

***edit re-experiment limiting to 20s each
start -7.2960v, end -6.6941v (68nF) 30.1mV/s -- 301pA/6.8 = 44.2pA ?
start +7.3356, end +6.7318v (68nF) 30.2mV/s -- 302pA/6.8 = 44.4pA ?
OTOH, if it is 300*6.8 = 2nA, that feels like the cap leakage i just measured instead

edit : if i use this tool http://www.learningaboutelectronics.com/Articles/Capacitor-discharge-calculator.php#answer. and reverse estimate the resistor, it shows that the estimated current is really 2nA. o my

did i get this right?


**edit, after going thru the schematic. it seems it might have been the mmbf4393 gate leakage, the combination of so many of them? after going all ape over noise, now it seems i have to go monkey over leakage current? with that in mind i am beginning to understand why they have Q106/107, to balance out the leakage current, and why the advice to sort the JFETs

JFET gate drives
Q104 -15v DCV 11100
Q106 +15 balancer?
Q105 -15v 2w/4w 1111111/0000011
Q107 +15v balancer?
Q113 -15 2w/4w 0000000/1111100
Q108 -15v DCV 00011
Q136 -15v DCV 00011
Q114 -15v DCV 00011
Q109 -15v 2w/4w 0000011/0000011
Q120 -15v 1111100

**UPDATE... i couldnt think of a simpler way to repeat and vary this experiment, so i tried removing zener VR106, and wriggling the Fwd/R switch
and it seems it is the switch. again i use 20sec interval
start -7.2998v, end -7.1710v (68nF) 6.44mV/s -- *68 = 437pA (exceed 10G input impedance)
start +7.4257, end +7.2213v (68nF) 10.22mV/s -- *68 = 695pA (approx 10G input impedance)
DIRTY switch !
i dont think i am going to entertain myself changing the switch so i will clean it instead !

[Kleinstein]

Two of the JFETs are used as a diode for overvoltage protection and also compensating some of the leakage.

The calculation is about right, it's about 2 nA.

However the current is changing sign. So this is not bias current from gate leakage but more like an input resistance that is not high enough. So this might well be leakage due to dirt on the board or at the relays / switches.

2 nA at 7 V gives an input resistance of about 3.5 GOhm - so well outside the specs.

If in doubt with the capacitor,  for a test you could check discharging disconected from the meter for something like 1000 s.

Hunting down leakage is a common problem in high impedance circuits. Not every isolator is perfect in the pA range.

[Kleinstein]

The input impedance just in spec ( 10 G) is OK, one has to keep an eye on this - this may change overtime, with soldering somewhere or cleaning it again.

For characterization one could also have a look at noise current of the input. That is do noise test with a 1-10 M input resistor and without and compare. The LTC2057 has quite some current noise - this might be a problem if high impedance ( >1 M)  signals are measured. In some AZ OPs the current noise can depend on the supply voltage - at least have a look at the datasheet.

Testing the Ohms ranges may be a goog idea if Fets have been changed. Though I don't expect big problems there.

If the fets at the divider were changes, the high voltage calibration (100 V range) might want a test.

A more comon mod might be adding isolation / shielding near the refference circuit. Here slow turbulent air flow can change temperature gradients and thus give small low frequency variations.  This might reduce noise in the 10 V range a little.