my noob journey to lower DMM noise (keithley mods)

[3roomlab]

completely bypassed input line from mechanical switch. input impedance +ve is slightly under spec @ 9G++, -ve is over spec, over 20G ?
it is as if a very small JFET leak favors +ve (too many JFET tied to -ve rail)

[3roomlab]

further "repair" of input impedance success

by swapping a 11v zener from VR115 to VR106 which i had suspected initially to have overheated from the short circuit accident. since VR115 did not need the pristine reverse leakage, it became the guinea pig for VR106. the input impedance is now over 10G ! hee hee, what a cheat, using the DMM own parts to service itself

plot input impedance vs 10v range input (68nF X2 cap)
thanks to alex nitin for this method 3 i would otherwise have no clue how to measure such low leakage

well this is weird, after ths above success, the input impedance returns back to 9G++
hmmmm ... do "senior" zener have such performance? esp when operating temp rises?
or it was sensitive to the IPA cleaning ... *confused*

**edit : due to the continuing frustration with the inconsistent 4mm banana socket, this is also BYPASSed with test leads now direct to PCB. and shaving off another small layer of noise.

[Kleinstein]

Leakage in the 10s of GOhms range is sometimes tricky. One thing that can have an effect is humidity: above a certain level, that depends on the material , a surfcare layer of water is forming that can contribute to leakage currents. So to a limited degree (e.g. 10-20 K)  it is positive if the circuit is warmer than ambient as this reduces relative humidity and thus formation of water layers.

It can take some time for IPA to fully leave some cracks or pores in the board material. So leakage can drift quite somewhat the first days after cleaning.

Chip internal leakage usually depends on temperature - so one can find leaky chips / FETs by heating them: if leakage get much hight with a 10-20 K temperature rise, the part is a critical candidate to look at. So leakage from inside the semiconductiors might actually be the easier part to locate.

As far as I see there are no zener diodes in the circuit that should contribute to leakage.: VR105/VR106 are bootstraped at the guard ring, not directly at the output. Only if leakage is very large ( > µAs range) this might give some contribution. One could check the voltage at the guard but I doubt this is the problem. This critical part in the overvolatage protection section is the optocoupler hold at low voltage (e.g. offset of OP).  AS shown in the plan I have, VR115 is just bypassing a resistor - does not make much sense to me, so there might be an error in this part.

[3roomlab]

well swapping the zener produced some weird impedance results, now even after warm up.

i think ima have to change them all

it is as if, the fwd/reversed zeners have to be matched in leakage when in the same net

**edit

[Kleinstein]

Without lables these graphs make no sense . What are they showing ?

The diodes should not be so critical as they are driven by the OP, not by the input signal. Only of they change the voltage of the guard this could lead to big trouble. The voltage at R122 would be an good indication - it should be small under normal conditions.

With the circuit around VR115 you have to check if the schematics is correct - I have some doubt there.

The diodes might be slightly sensitive to light, so keep the cover closed or at least avoid intense light.

[3roomlab]

ops sorry. that plot is Gohm vs voltage of 68nF discharging into input impedance

VR115 circuit is correct, VR106/5 is reverse

(i updated some schematic in K2000 repair thread here using kicad, https://www.eevblog.com/forum/repair/repaired-keithley-2000/msg814435/#msg814435)

after playing around, i think the graph is responding to p-p value self noise of DMM? if i change the sample width to measure the volt-drop/sec of the capacitor, the plot also changes the wave shape

did i make mistake?

[Lightages]

I think it is time that Dave make this ahole's information public. He seems intent on being as public an asshole as he can. So let's all know who to send the emails to.

[Kleinstein]

The stange zagged curves could be just an artefact on how input resistance is determined. Could be something about rounding / digits.

With the input resistance is might be more usefull to look at it as input current versus voltage. By definition there should be only one input resitance as the sloop of input current versus voltage. It might be normal to get silghtly higher input currents as the voltage approches the 10/12 V nominal input limits. Finally the zener diodes set in slightly soft - thats normal and hard to avoid without bigger changes. The influence from the zeners will first show up as current to the guard OP - so you can check that.

As for the cause of the rather high input currents, I still suspect dirt on the board and maybe some of the changed FETs. Also the OPA2140 might be a candidate as it runs relatively hot - this change may not have been the best choice.

[TiN]

Hence I hold 3roomlab for all his tin-cap nuttery. I mean look at that poor 2000...it's just as insane as it gets.

My version follows, copper-hat for 3458A's A9 to test air current issue (~1ppm jumps)



Proven useless, still doing jumps. ESD film under module is to make sure copper bottom film not touching A1 PCB.

[Macbeth]

I think it is time that Dave make this ahole's information public. He seems intent on being as public an asshole as he can. So let's all know who to send the emails to.

Oh no!! @3roomlab, I am 100% certain this message is not referring to your good self, but a miscreant known as mojo-chan. The deleted post leaves this one without context. 

(BTW, it appears that the mojo self-doxxed in all his posts so no need for Dave to do that. I'm ashamed for my country he apparently lives in Portsmouth, UK)

[3roomlab]

@ macbeth, thats why now i like to delete my own old posts. but i do leave some relevant ones.

@ TiN, i think 3458a are so well designed, i doubt they have noise problems like keithley. well at least you have real copper hats  . and i bet 3458a dont have AGND lines that measure 0.3ohm per inch . OTOH, if you keep autocal-ing, doesnt the 3458a work normally? but as it is, i think it does more good for impeding air currents.

today i tried some more tinkering. and i found something interesting. my version of PCB have these things missing (gif 1). i wonder what is the purpose of the JFET sitting in between?

i then scoped that line. ref C254 pin3 U132, vs U166 pin6. 10v range input is open, and input is shorted. amongst the signal, is also what seem to be a bunch of self noise as the opamp self amplifies

there is also the observation of pin6s of U132/166. when i try to read a battery. the yellow signal is suppose to be to A/D? but the noise, and there i spotted like somehow, the autozero interfering with the A/D signal, tiny spikes. this noise coincides with the way the NPLC/AZERO cycles the MUX (see the jpg of Q104)

and i also spotted a somewhat 1 inch trace AGND, and that somehow is 0.32ohms. making some noise to sit onit. this AGND is a new discovery running amongst the A/D MUX, which needs to ref right back to VREF, and here yet another AGND flapping around at around 0.25ohm between MUX and VREF. using analog scope, at 1mV/div, the probing this net turns a solid trace into a fluff, but the actual p-p cannot be seen properly (lousy scope i have)

i am tempted to add some kind of bypass, but it will just wreck the MUX signal for A/D. anybody have anyideas what to do with such kind of signal line? if magically, ferrite beads could appear in the copper line, would that be a possible solution?
the blue trace U132, is suppose to compensate AD711, but at the same time it injects the compensation signal as noise

sometimes i think, why is it so hard for them to put proper AGND plane? it is so weird they did the planes for the 2 digital sections. but did nil for analog. but in any case, im glad i got this unit for cheap

edit**
A/D MUX shortening of AGND return path, test plot. warm up 1.5hrs, 100mV/1NPLC/AZERO=on
plot 1446
3600samples STDEV 125.92nV, p-p 918nV
500samples  STDEV 119.25nV, p-p 659nV <--- quite a large drop in p-p noise

plot 1516
3600samples STDEV 122.91nV, p-p 822nV
500samples  STDEV 123.25nV, p-p 755V
looks like STDEV is under 130 for good? and p-p noise is under 1uV for good?

[TiN]

Copper pours on analog PCBs often could cause more harm than good, by adding capacitive coupling between sensitive signals. So more copper is not always a good thing.

[Kleinstein]

More GND is not allways good. Also the resistance of the lines is not that critical, if the GND is used as a star ground -then it is important not to have some extra connections even if both a labeld AGND.
Especially those lines withou a solder mask are usally used as a guard to reduce leakage - there is only minute currents flowing there.
Measuring very small signals with the scope is often tricky where you have the GND connected - so the low level signal you find on AGND traces may not be real.

The stage looking JFET in the first picture is a kind of current limiting. It may have turned out that it is not needed - pissibly due to slightly different shitches (U163 and 129)

[3roomlab]

Also the resistance of the lines is not that critical

true, it only affected few tenths of uV/PPM. i am going to try more thorough cleaning, i hope i dont strip off the PCB traces and parts  . i think i really need the input impedance back up over 10G, and prevent the NPLC/AZERO signal noise to exit into INPUT ...

**edit
as AGND is shortened more, the log results tend to appear more repeatable/predictable, instead of being plagued by random peak spikes (but i guess that is my only way of seeing it with my limited experience)

eg : now even disable AZERO, it also falls under 130nV and under 1uV pp noise (with similar looking result as AZERO on)
plot 1835, 100mV 1NPLC AZERO=off
3600samples STDEV 127.49nV, p-p 891nV
500samples STDEV 125.97nV, p-p 654nV

[3roomlab]

looks like i got it right this time. bought a really fine painting brush to "dig" under the SOIC/SOT23 with IPA (M-ohms vs volts plot)
again, the NPLC control signal seem to leak into the measurement side. and strangely, lower voltage seeming to give lower impedance.

[Kleinstein]

It may take a few days for the last traces of IPA to be evaporated. It also takes a little for the system to warm up all the way - this can also effect the input currents. Warming reduces surface leakage but increases semiconductor leakage.

From the circuit there should be no difference between the 10 V / 1 V and 100 mV ranges - for the K2000 amplification is only changes in a separate stage after the input buffer. It could be just the sequence.

[3roomlab]

after abt 5 hours of warm up and rounds switching around capacitors, the impedance did increase ... by alot.
but at least, now the impedance vs volts are of the expected lower volts = higher impedance curve.

edit **
@34nF 15v 10s drop = 5.33mV/s, = 181pA, = 61.1G @ 11.1v
reverse @ 204nF 18v 10s drop = -1.39mV/s, = -284pA, = 39G @ -11.1v
the reverse character is slightly weird that it required alot more charge (4 to 6x) to make it past -11v.
is this what originally K2015 is in terms of impedance?
if so, it would mean that either i need to dampen the hyper sensitivity, or enhance it further with more attention to lowering of creepages?

(plots are Mohm vs Volts)

edit*** more testing
im not sure if im doing this right, but i have no other reason (or lack of reason)  to think there could be something wrong
@68nF 10s drop  -1.364mV/s, = -92pA, = 50G @ -4.70v
@68nF 10s drop  0.874mV/s, = 59.4pA, = 82G @ +4.93v
@68nF 10s drop  -0.616mV/s, = -41.9pA, = 45G @ -1.88v <---- weird
@68nF 10s drop  0.306mV/s, = 20.8pA, = 92G @ +1.92v

geeez 82G impedance

[sync]

This is what I get on my old and self-repaired K2000 by measuring the voltage drop over a 10MOhm resistor.
+10V: 63pA -> ~160GOhm
-10V: 15pA -> ~670GOhm
0V: -25pA bias current

To do the measurement a (short time) stable voltage source is needed. Connect the voltage source in series with the resistor to the meter. The resistor should the as near as possible at the HI input. Short the resistor. Read the voltage on the meter. Remove the short and read the voltage again. The difference is the voltage drop over the resistor.

[Alex Nikitin]

im not sure if im doing this right, but i have no other reason (or lack of reason)  to think there could be something wrong
@68nF 10s drop  -1.364mV/s, = -92pA, = 50G @ -4.70v
@68nF 10s drop  0.874mV/s, = 59.4pA, = 82G @ +4.93v
@68nF 10s drop  -0.616mV/s, = -41.9pA, = 45G @ -1.88v <---- weird
@68nF 10s drop  0.306mV/s, = 20.8pA, = 92G @ +1.92v

What type of capacitor are you using?

Cheers

Alex

[3roomlab]

@Alex, i am using this http://sg.element14.com/epcos/b32922c3683m189/film-capacitor-0-068uf-305v-20/dp/2334253
although i did not specifically note the voltage, 1 of it left from yesterday still carried about 7v of the test voltage of roughly 7.5v

some notes on noise after "restoring" the high impedance. it seems to be more sensitive to it self noise, more notably sharp spikes and a AZERO beat frequency (abt 350-400sec per cycle) which is now measurable by itself. plot 1206 azero off (STDEV 138nV, pp 959nV), plot 1052 azero on (STDEV 152nV, pp 1319nV, note sawtooth pattern). plots are nV vs seconds. in both plot the 3 "tin hats" are in place, temperature under the "hat" is @ 42.2C. 2 other plots also show similar beat freq and high spikes like plot 1052 with azero on, so it wasnt a coincidence.

since i couldnt see any other option to single out this spikey noise, i thought i just try re-running w/o the main "tin hat". and that, surprisingly reduced the noise. which i suspect might be just a temperature induced problem, w/o the tin hat, the analog section is now floating with the rest of the DMM temperature @ 40.2C. i am not sure if the tin hat have any electric field that could influence the guard, itself is tied to AGND, or maybe there should be a separate guard voltage for "faraday cage"? plot 948 azero off, (STDEV 127nV, pp 880nV), there are also 2 other plots with similar low noise, so this is not a coincidental capture either. it seemed like the same problem as the BJT popcorn noise encountered before, higher temperature = more noise.

with the hat off, i then also tried with AZERO on. this gives the plot 1139 (STDEV 124nV, pp 908nV exclude first 100 startup samples). it is purposely sampled at an odd 3Hz to see if it will pick up any beat frequency, but it appears maybe the AGND + tin-hat is the problem creating more noise,as there is no beat frequency visible and there is less serious wavy drifting.
**edit, the next plot is also a stable similar plot, looks like i can use AZERO perma-ON again as it has somewhat no percievable added noise

[3roomlab]

This is what I get on my old and self-repaired K2000 by measuring the voltage drop over a 10MOhm resistor.
+10V: 63pA -> ~160GOhm
-10V: 15pA -> ~670GOhm
0V: -25pA bias current

To do the measurement a (short time) stable voltage source is needed. Connect the voltage source in series with the resistor to the meter. The resistor should the as near as possible at the HI input. Short the resistor. Read the voltage on the meter. Remove the short and read the voltage again. The difference is the voltage drop over the resistor.

wow ! such high impedance !
i shall try it when i have parts. thanks for the info

*edit. what was broken in your DMM?

[Kleinstein]

One should not convert individual inut current deadings to input impedance. The input current is from two sources: an bias current plus the current from the input impedance. So the -63pA / +15 pA at +-10 V is more like the -25 pA bias plus a 250 GOhms input resistance. Still good and about the right order of magnitude.

Higher temperature usually gives more noise, but this usually is not that much - usually something proprotional to temperature in Kelvin or the square root of it.  One exception would be the leakage from semiconductors and the current noise connected to this. With a shorted input however current noise should not be important.

To check the effect of the AZ phase it might be interesting to check a non zero input signal. A simple battery at constant temperature (well insulated) gives a very low noise source. With a non zero voltage, the AZ phase might introduce extra noise / errors and it can be more sensetive to extra capacitance.

[3roomlab]

wait a minute, 250Gohm? is that the expected of bench DMM? that would mean my impedance is still too low?

hmm i dont understand what is azero phase?

**edit
i think i will add this info for other keithley users who are interested in the use of repeating average to extend NPLC. for comparison, the left plot is 1NPLC x 25 REPeating average (math wise it is 25NPLC), the right plot is NPLC5 x 5 REPeating average (math wise it is also 25NPLC). however @ 10v range, resolution down at uV level is very poor, so by averaging further a low resolution 1NPLC with higher pp noise, it will result in a weird "coarse" output, but an averaging of a finer 5NPLC resulted in a "finer" plot which resembles a more normal noise plot. maybe someone with more mathfu can give a more proper explaination, but in any case, this is again to show repeating average is usable as NPLC extension

**update
comparison of NPLC 10x10REP on left (~NPLC100) [STDEV 349nV, pp 2542] vs NPLC5 x 20REP on right (also ~NPLC100) [STDEV 316nV, pp 2325] . in this comparison, it seems the "finer" noise plot is on the right. NPLC2 x 50REP will also be done for comparison

edit** sanity check of NPLC x REP. i overlay a NPLC10 10v plot on a NPLC2 x 5REP 10v plot (~NPLC10). and the resolution lined up on the dot.

[Kleinstein]

The specs of the meter are only > 10 GOhm. But much of the resistance is typical due to surface contaminations and similar leakage. So i can vary a lot from instrument to instrument. So the garantied miniumum is 10 GOhms, but the typical instrument will be much better, like in the 100-1000 GOhms range. However it might just take a bit of humidity or a little dust to change these values.

The Auto zero (AZ) works by switchung the MUX from the signal to GND for a short time. Here having a signal near GND is the easy case for the AZ. With a signal significant different from 0 it gets a little harder, as delays and possibly lossy caps can add errors. So to really test the AZ mode, one should do a test at higher voltage (e.g. 9 V battery).

[3roomlab]

progressing to rebuild another DC regulator to replace the temporary unit now inside, i need to find out if this is the correct way to put the zener for gate protection?