my noob journey to lower DMM noise (keithley mods)

[TiN]

3458A's manual state that NPLC over 10 are average of number of NPLC10 samples. Might not apply to K2000 though. K2002 have NPLC up to 50, but I barely ever see any big difference between 50 and 10.

I had 2001 in works to replace LM399 with LTZ, but it's not working right (oscillates like crazy ) yet.

[3roomlab]

3458A's manual state that NPLC over 10 are average of number of NPLC10 samples. Might not apply to K2000 though. K2002 have NPLC up to 50, but I barely ever see any big difference between 50 and 10.

I had 2001 in works to replace LM399 with LTZ, but it's not working right (oscillates like crazy ) yet.

hmmm i assume, if all normal electronic noise are quite similar, giving similar bell curve w/o much introduction of external noises. in theory, the same math should be applicable? it is all basically sum and average, and then summed and average (probably with increased bits of error, and more samples reduces or makes the error more visible)

r u not using your spare LTZ in it? the 2001?

edit** ok now i guess i know why max NPLC for K2015 is 10, i suppose K20xx design is based around a similar framework of many popular bench DMMs of how to handle NPLC. your information about how 3458a handles NPLC 10 pretty much nails it that "REPeating average" can "multiply" its base NPLC10 to NPLC 1000

[TiN]

I did use my module, but 2001 have not simple way of reference driving, it's part of few other reference generation driving on ADC module, so need debug it a bit more, to understand how it works.
Simple "remove LM399, pop +7V from LTZ" did not work. I posted about it in 2001 thread some time ago. Anyway, it's offtopic here. Upgrading 2000 with LTZ should be much simpler job, but I'm not going to do that. 

[3roomlab]

hmmm zero experience with 2001, i would need to tinker to know more (my electronics theory is terribad). maybe it have the same SOT23 BJT problem?

**edit. attached pic, showing the extent of the PCB topside mods. it looks quite hideous, flux "pee" all over and not very orthodox, hope it can give some ideas for other tinkerers. ceramic SMD caps used are 1210 (esp bottom side), for lower ESR. the first noticeable noise improvement are from them 10uF replacing the 0.1uF (see pic in post #16). topside most noticeable improvement was reduction of generic popcorn noise (identified by kleinstein) which came out of the SOT23. sidenote : the 1206 10uF bypasses added do not seem to give big noise improvements, but they are left there anyway.

** edit 2 : testing NPLC 100 logging (plot 1722) total 19hrs
STDEV 73.79nV.
SKEW -0.2006
KURT 0.6328 (lotsa fluctuations !)
18hrs voltage drift from 1st hour mean is -3nV
total known DMM internal temp change 0.2^oC

being new to the world of NPLC 100, a XY plot shows me all the crap parts of the log clearly. NPLC100 sensitivity makes NPLC 10 looks like a 3.5digit DMM. and i clearly need a good AC isolation device as tiny fluctuations can cause big changes in long term readings and make a few days worth of log go to waste

quietest 1hr block of 100NPLC (of the 19 hrs logged)
STDEV 60.38nV
SKEW -0.0231
KURT 0.0490

[3roomlab]

with the new understanding that "REPeating average" function can be used as a NPLC multiplier. today i try this DMM ability in a way to compare with the new known noise characteristics of the modded K2015 @0.1v range (SDV about 155nV @ NPLC 10)

the results is quite astonishing (or at least to me). due to the shorter NPLC cycle, i could also sample at a higher rate of 2Hz :
[NPLC1*10REP], 100mV. sampling 2Hz. azero = on (7200samples/hr) + REL adjusted in xls sheet
SKEW -0.080
KURT -0.174
STDEV 151.49nV
TRIMMEAN 1.002

even with a skewed start-up into a stable plot, the SDV obtained beats my usual 155nV. this may mean a 1NPLC * 100REP may even beat my last 100NPLC plot test plot (which means instead of using 6.6seconds delay done in the test run, on 1NPLC*100REP, it would take about 2.6seconds)

[Kleinstein]

With 1 NPLC Bandwidth should be 25 Hz. Noise goes up with the square root of the bandwidth and down with the square root of the number of samples for areraging. So there is no big difference between using a longer time for each conversion or more averaging. The only difference is doing averaging analog or digital - so no supprise to see no real difference.

The overall data rate might be different because auto zero also takes some extra time for switching.

Things can get a little different if there is drift or noise that is stronger at low frequencies. Than going from 10 NPLC to 100 NPL may give less reduction and the repeated autozero may also make a difference. However here the main noise source is essentially white noise from the LTC1050.

[3roomlab]

a little more improvement again. with some bulky heatsink mods. this reduces the internal air temp to 41.9^oC (without using any fan circulator). and the DMM is now having to "stand" on its side upright (with the orientation of the banana jacks below). the large heatsink are glued to almost the entire bottom side (which is now vertical, which becomes a large radiator of sorts)

this produces the 0052-44 plot. [2NPLC*5REP] 0.1v scale @ 1.5Hz, 5400samples/hr (azero=on, manual REL)
STDEV = 144.56nV, SKEW= -0.024, KURT=0.166, TRIMMEAN= 0.999
first time ever breaching 0.15 barrier. in a previous test run, 1NPLC*10REP produces a plot with about 160nV SDV.

[lukier]

Remember that LM399 is sensitive to orientation Adding some extra insulation might help the internal header do its job.

[3roomlab]

and so ...

the itch returns ...

why does 10v range have so high a pk-pk noise?

dont turn it on ... take it apart !

and back to square 1, step by step tweak and log more noise ...
in order to reliably improve usability of last digit, i feel that % error of 90day PPM drift/error margin should not be exceeded by more than 20%.
this means that 0.1v and 100v ranges always fail this criteria. except for 1 special log 0.1v @ 100NPLC, dropping down to only 8.9% ...

but all these are now history as the PCB is yet again tweaked, new logs are on the order for next few days ...

edit * minor changes are done to the DMM again. in this round i took some time to look at front and rear disparity in readings, which has quite a difference. which could mean a problem in the switch, or it could be the socket, o boy
0.1v 1NPLC test run, STDEV 0.46uV, pp noise 3.36uV. PPM range 4.6, pp noise PPM 33.6

@1NPLC if we treat this as the base noise (w/o averaging to 10NPLC), this could be a better representation of what noise i am trying to solve in the machine ... maybe

edit ** due to a lack of low thermal EMF connectivity parts on hand, in this next minor mod, i solder a jump cable to short the sense HI-LO. this bypasses the switch, banana and internal cable interconnects. in a short looky look, the 2w ohm indicates front/rear ohms as being compensated internally for approx -0.07ohm/-0.1ohm respectively. now we shall go back to logging this variant. (short note : the LO is connected to AGND as well, while HI i used a leg of R113. this log will probably tell, how much thermal noise the front end connection has hopefully

[3roomlab]

and yes ... i made some more improvements again. and again, in a area which should not seem to influence final noise. but it did 

as with the previous looky looky poking around, i had some thoughts that the zener (VR107/108) was a trouble maker. i had some spare zener (panasonic DZ2J series, 4.7v. SOD323, approx Tja = 250^oC). the est current thru the zener is about 4-5mA, power dissipation is approx 0.025w, = Trise of abt 6C

based on the last 3600-7200 samples of plot 2213 (this is a 2Hz plot 7.2k samples), we are looking at 1NPLC plot (yes the super noisy ones), we have a STDEV = 0.392nV (with stock SOT23 zener, STDEV was average 0.45-0.5uV BUT for a flat 3600 sample plot). i thought shit, 7 year old zener, must be noisy as crap!

and the MAX-MIN p-p noise is now 2.9uV as opposed to average over 3.4uV

these cheap SOT23 zeners are suppose to provide 5v to the LTC1050 zero buffer opamp, they are changed now to 9.3v using 2x 4.7v.

come to think of it, there are 2 more 6v SOT23 zener at the LM399, they are suppose to be giving +/- 14v VREF. what the heck !?!?

so maybe i should get some 5v VREF zener (LM336?LM329?) and further enhance the zero buffer. but what should i replace the 6.2v with? there arent any VREF 6.2v zeners.  ... 1n829 ?

( if the noise of the 1NPLC is reduced more, it will look like a 10NPLC plot, when i first logged w/o any mods. it would be hilarious if NPLC1 has same noise profile as NPLC10)

*** i guess i was tired, and was poking at the DMM and shorted something. now its not happy with me ... mod -> becomes repair

[3roomlab]

as i was going thru this circuit (VREF section of K2015), the workings of how it manage to bump the LM399 into both a + and - 14 volts just doesnt come to me. i cant seem to visualize which resistor is being used to 2x gain the opamps? (or maybe i lack of sleep again)

[Kleinstein]

This circuit part is still relatively easy:
U139 is producing the positive voltages and U140 is producing the negative ones.
The transistors zener diode are just there to extend the output range and reduce the power disipation of the OPS.

The inverting input of U140 is a virtual ground - so the positve side divider works towards this virtual ground, not real GND. Besides saving one high qualitiy resisitor this alows sensing GND with a low current line. So it's a rather clever circuit.

p.s. The resistors A4 ... A14 are not part of creating the ref voltages, but likely part of the ADC or amplification before it.

[3roomlab]

ok let me try to understand
so U139 pin 6 current drains so that current thru Q130+VR113+A1+A2 show a voltage on pin 2 to equalizes with pin 3 (LM399 VREF)

then on the flip side U140 pin 6 current sources so that VR112+Q129+A4 equalizes virtual zero pin 2 to actual zero pin 3? but because pin3 is a float, does it mean U140 is the key of pivoting both +/-14v around the virtual zero? (so A1/2/3 balances a "see-saw" with A4? so if resistor value drifts, the balance skews? so it relies alot more on the A1/2/3/4 character for stability?)

thanks for deciphering

on a side note, R315 seems of no use, wouldnt that add noise?

[Kleinstein]

The relative stability of the resistors is critical - this is why they are in an array to have close matching TC and similar drift.

The positive +14 V output scales with (A1+A2+A3) / A3. The -14 V reference scales with A4/A3.  So they depend on the resistor reatios, but not more than needed.

R315 is needed for startup. Initailly the +14 v is still at zero as it is derived from the reference. So there is a little current needed to bring up the reference so that the ref output can than deliver more current. It is not that much current comming from there, so the influence is small. There is no significant noise coming from R315 - if at all it gives a slight dependence of the reference voltage on the +15 V supply. But at about 1 Ohm of output impedance of the LM399 and 100 K for R315 this is only a very small fraction of the supply that enters. There would have been ways to avoid this, but it's nothing to worry about.

[3roomlab]

ah i get it now

matching the resistors exactly will be a tough nut to crack

[Kleinstein]

Yes one scale the reference circuit to higher voltages if one wants to. However if it is to drive possibly capacitive loads, a modified version, more like a small pwer supply is probably better.

[3roomlab]

with slightly more understanding of what is going on with the VREF section, i wanted to try to simulate and find out what possible noise source dominates the section. after several iterations of simulations, i think these few pics give a close example of what is happening (probably)

pic5- knowing pin6 is driving @ 8.9v, we replace the zener to be represented by a resistor (there seems to be some problem with simulated zener). so we derive R1 noise to be possibly 40uV. dominant noise is from VREF

pic6- by subjecting pin3 to a LPF (VREF feed), we get a lower noise, and a mix of noise from all sources.

pic7- it appear R10/R9 need to go ape to get really low noise, and it may be possible to replace 6v2 zener with actually a resistor.

unknowns : reduction in VREF noise mean reduction in DMM reading uncertainty? (especially w/o intervention of NPLC/averaging).

[Kleinstein]

The dominant noise source is likely the reference chip (LM399). So don't expect to much from reducing the noise of amplifier.

There will be a littel bit of noise from the 6.2 V zener used for level shifting, but here the OP will compensate for most of it, especially the lower frequency part. A capacitor (e.g. 1 µF) in parallel to the 6.2 zener could reduce the higher frequency noise, where the OP may not be as effective in compensating it. Alternatively 2 or 3 LEDs in series might be an lower noise alternative to the zener (no stable voltage is needed, just about 4-12 volts). Just a resistor and capacitor in parallel might work to. Without the capacitor it might be to slow and PSSR will be not that good.

Filtering of the reference might reduce higher frequency noise (e.g. >100 Hz). This might help a little at the short integration times (1 PLC), but less to nothing at long integration times. It is just very difficult to filter out low frequencies.

[3roomlab]

The dominant noise source is likely the reference chip (LM399). So don't expect to much from reducing the noise of amplifier.

There will be a littel bit of noise from the 6.2 V zener used for level shifting, but here the OP will compensate for most of it, especially the lower frequency part. A capacitor (e.g. 1 µF) in parallel to the 6.2 zener could reduce the higher frequency noise, where the OP may not be as effective in compensating it. Alternatively 2 or 3 LEDs in series might be an lower noise alternative to the zener (no stable voltage is needed, just about 4-12 volts). Just a resistor and capacitor in parallel might work to. Without the capacitor it might be to slow and PSSR will be not that good.

Filtering of the reference might reduce higher frequency noise (e.g. >100 Hz). This might help a little at the short integration times (1 PLC), but less to nothing at long integration times. It is just very difficult to filter out low frequencies.

hmmm ok i will try LED once i get parts to revive the DMM
** edit .. interesting question: did anyone characterize their drift? lol

[Kleinstein]

The zener diode is only there to shift the ouput range of the OP, to get the 14.x V output range. So drft of zener diode or a replacement would not matter at all - anything in the 3-20 V range should work. Just the noise of a typical zener diode may not be optimal.

LEDs forward voltage is temperature dependent, similar to normal diodes. There is also a good chance to see some drift towards lower voltage as the LED ages and more non radiative recombination paths slowly get added. So a LED won't be long time stable.

[Kleinstein]

With noise it does not hep very much if you reduce the small contributions to overall noise even further. At least in the 100 mV and likely also in the 1 V range the main contribution to the DMM's noise is the input buffering amplifier (LTC1050). So even if all other nosie source would be eliminated you can only expect something like 10% less noise.

In the few cases one needs to measure a small low noise DC voltage, I would consider an extra external preamplifier. Especially if you can live with a lower CAT rating, noise can be much smaller (e.g. a factor of 10 or 20). With modern AZ OPs this is not that difficult any more.

[3roomlab]

power sub-board is running. somewhat too cool it seems (iirc old stock heatsinks run at approx 53C?)
+5V A/D rail, +8.61v in, +4.99 out
+ analog rail, +22.4 in, +19.4/+15.2 out
- analog rail,  -22.6 in, -19.5/-15.4 out
measured ref to AGND TP102 + old TO220 legs spots
and now to replace next group of components
must be a strange sight, a crude "plugin" board
interesting part about this temp sub-board idea is that, the heatsink has magnets which further (try to) interface the heat out to the chasis (seperated by some kapton tape). so the capacitors are no longer "harassed" by the VREG . hopefully this will also further reduce internal operating temperature (shaky hand photo yuck, but you all get the idea). however it may also add instability. cos there is much more temp diff in the inside air now, but i dont know, lets see how it pans out.

[3roomlab]

continuation...

replaced 6x mmbf4393 (Q 104/105/113/108/109/120), 1x LTC2057, 1x OPA2140, 2x BC560
the E14 LTC2057 arrived with a dented pin  (see pic) such a sensitive IC ... ... i should replace it? o nvm, its just a bit of experiment
firing it up, the reading is somewhat crazy, there is still a residual float voltage which i dont understand its origin (inputs open). example : 1v range open, the jumping residual is also about 1v LOL ! how can this be? !!!
when inputs are shorted they behave like shorted, and there seems to be no components heating up especially because of this short 

anyone want to throw me some ideas where this residual float could be from?

but even with such a "flaw", the shorted noise @ 1NPLC 100mV even without top cover on, is impressive !
looking at the running numbers, it feels like i am running NPLC10-ish. i shall update plot when log is done

the FLIR shows the temp overview, with peak spot 41.7C on the OPA2140. the dark cluster (TO92) diagonally above it is the zero-buffer power regulation going to LTC2057. and further diagonally is the AD706

[3roomlab]

i am excited to say what looks like a interesting big leap in noise reduction (or somewhat).

this is NPLC 1, 100mV, AZERO=on, no REL/AVE. top cover is open (with slight draft)
sampling 2Hz, 3600samples/30min

on checking previous logs. the "width" p-p drifting about seems to be as low as old NPLC 10 log (if not, possibly lower than 1uV). this is quite fascinating. the 2 stars of this experiment 1) http://www.ti.com/product/opa2140 2) http://www.linear.com/product/LTC2057
(and possibly helped from an extra stage of linear regulation? maybe?)

due to suspicion of another fault lurking somewhere, i will fall over into spasm if later i find that the unit cannot measure any voltage at all  but only measure shorted noise !

** edit .... i couldnt help but laugh at myself when the plot appears. best pre-xmas surprise present?
again 1NPLC conditions, but covers closed, log restarted same 3600samples/30min
this is just crazy, before this mod, 1NPLC noise is like bloody 3.5uV p-p

[3roomlab]

  the result just blows myself away 
1 NPLC 100mV AZERO=on, no REL/AVE. ambient 27.8C, DMM internal 40.4C, hum 67%
3600samples @ 2Hz (30min)
AVE : -2799.82nV
skew: 0.1187
kurt : 0.0209
STDEV : 133.98nV (SHIT !!! thats really low) (145nV)
p-p : 893nV (986nV)

EDIT : compared to my previous NPLC 10, this bloody NPLC is LOWER in noise than my OLD log (in blue) ! SHIT !

edit ** mini blower fans have arrived 12v 70mA. to aid in internal air circulation. the current repaired logs are w/o fan.
internal fan added plot test, and it appears there is yet another component having ability to send out tiny spikes (plot 2306). with this plot,
STDEV : 135.42nV,  p-p : 938nV. internal temp 41.3C.
with the p-p narrowed, the tiny air current seem to be able to make fluctuations in the plot