my noob journey to lower DMM noise (keithley mods)

[Kleinstein]

Just testung different capacitors in the DMM is tricky: Even if you know about the circuit, it is hard to predict how high frequnency "noise" (more like ringing) on the power supply will change. Its also not clear how signals from the supply influence the result. The caps can also change the amount of electrostatic coupling, as they may work as a lectric shield. As a third effect they can change the thermal effects. So outcome can be rather random: put the DMM to a different place or orinetation and results might be different.  If at all one would need to use a good scope to probe the supply, and go for low noise / ringing on the supply first.

With just random tests there is not much to gain.

The OP change in the Keithley that TiN did is more like a lucky find of a minor design flaw. If you have a circuit plan this is sometimes possible, but not every low cost OP is a problem, usually they are the less critical ones. In old times HP used the JFET pairs - they are quite good compared to modern OPs, though the OPA140 comes close in some respect.

With the 3457 I have not seen am obvious weak spot - except for the whole concept of using only a +-3.5 range for the input amplifier, and not having a x 1 setting. So I am afraid there is no easy improvement.

[3roomlab]

@ lukier, sorry abt wrong link, the gold is 4mm stackable (its somewhere in the same web "shop"), see pic
yes i have used the bare copper wire before, but i have trouble in contact consistency, so i changed to those.

[3roomlab]

keep calm and log some more DMM noise !

** update today i did another mod, having the L104 AGND return using a different AGND node. the start up is compared in a 3 in 1 plot (light blue plot #1614), it also came with a huge anomaly near the end lol

red plot uses similar L104 AGND topology but tapping on diff node

magenta is L104 WITHOUT its AGND "shortened"

2nd plot comparison only use the 2 with AGND shortened. black = Nov15 mod, red = Nov 14 mod. the newer mod seem to warm up to more reduction in noise than the previous version.

if 1 were to think of this as a design challenge, you could see it as, how to make limited changes to a noisy circuit which you cannot change the already fabricated PCB design?

[3roomlab]

it is time to reel in the fish nets 

6 plots are done by this time. the results are marginally better, but is plague by a new type of noise pattern. all plots are 100mV 10 NPLC @ 1Hz sampling, trafo temp : 47.5^oC

plot with the least STDEV (0114)
AVE : 0.514 (uV)
SKW : -0.066
KRT : 0.207
SDV : 0.187
ADV : 0.148
TRM : 1.002
(3 set of plots consistently falls below 0.2uV SD)
the 0.187uV number has been showing up and seem to be the smallest SD limit with the current shoddy ghetto-ish setup. in comparison, alex's SD was 0.19, my own old logs averages around 0.21-0.27.

plot with worse STDEV (0214)
AVE : 0.512
SKW : -0.145
KRT : 1.997
SDV : 0.287
ADV : 0.206
TRM : 1.005
(3 sets are plagued with farty noises  )

as i have observed previously, the noise are always 1uV high, in this case, they are 1uV pk-pk. but the dippy noises are missing in all 6 plots (now i know for sure why kleinstein say it looks like popcorn noise https://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-14-01-00-00-80-75-78/Popcorn-Noise.pdf). there are now "farty" blobs of 1uV p-p stuff, however it could be due to large sample interval, that these are also multiple tiny popcorn noises      .

as i looked thru the previous mod, i found some soldering errors. made further changes/corrections (mod 16Nov plot in orange). and did a new log run. 2 temperature sensor are added.
in this mod, multiple 220nF SMD are added on top of the normal bypasses
log start : c156 cluster 27.9C, transformer 27.4C
60min : c156 cluster 44.4C, transformer 40.1C

4th hour
c156 cluster 46.2C, transformer 43.3C
AVE : 302.65nV
SKW : 0.076
KRT : -0.004
SDV : 186.87
ADV : 148.73
TRM : 0.996

[3roomlab]

i return to the "modding-board" today to try a different approach to counter the dippy/peaky/popcorn noise. as observed in many logs, they seem to appear more aggressive over a certain threshold temperature. i dug up a tiny dc fan from a celeron CPU, good old nidec 12v that only consumes 0.06A. i tied this fan to the 7v raw rectified rail (powering the communications), it consumes about 31mA. the small fan is mounted above the cavity of the 2 transformers, it draws air upwards cooling the trafos first, then some air turbulence would circulate thru the rear banana PCB cavity.

in addtion, i wanted to see, what will happen if i removed ALL the major trace "shortening" runs but left L104 and all the modded bypass caps. and this is the warm up plot result (0.1v, 10NPLC, 1.25Hz).

start log- 28.3^oC, 1hr - 40.2^oC. with active air circulation in place, the temp diff between PCB and trafo is only 0.3^oC (compare to last log, PCB area temp after 1hr is 44+)

based on this observation it would be interesting to see what would happen if i use a mini laptop sink blower fan. it could create a large turbulence over the PCB area.

** edit -- i believe i have found the source of the noise. mmbt 3904 / 3906. by using a soldering iron adjusted to 100^oC, i was able to heatstress the part and re-create the signature 1uV peak/dips (@100^oC, the peak dips go on forever !). but in an attempt to repair it, i think due to my lacking of SMD skills, i may have overstressed the package, and the problem resurfaces ... during operation, the 2 particular BJT operates at rather high temperatures of 60+++ ^oC

edit ** comedy run, after giving the SOT-23 a few taps, i  could hear a click. i thought i broke the SOT 23. but it appears the looks more stable now ... o my

via further simulation, the 0v buffer section draws direct raw +/-23v dirty DC, using the PNP/NPN pair, supplies constant current of approx 4.5mA to LTC1050 shunted by a series of 6.6v zener. the simulation suggests Q110/Q111 dissipates 100mW. this then calculates to a Tj of approx 100^oC+. isnt this too hot for a tiny SOT-23?

[3roomlab]

i made some interesting progress today. by temporary modding the zero buffer section with TO92 BJT and adding additional bypass caps. however as it is a try and see test. i only replaced 2x 2N3904 for -ve rail (unfortunately, i used made in china jellybeans as these are what i have at hand, a bunch of BC550C/BC560C are on the way to me, i am lucky to find some in RS components).

PCB air 43.2C, transformer 43.8C, the below stats are from sample 500-4500) 0.1v 10NPLC @1.25Hz
AVE : -0.140uV
SKW : 0.093
KRT : 0.229
SDV : 0.19008, SDV under 0.2 ! YAY !
ADV : 0.14991
TRM : 1.008
( the warm up appears fast due to the gear being already warmed. the best test scenario with SOT23 is so far SDV of 0.179uV, after which heat demon takes over after 2hrs+ and everything goes over 0.2 SDV)

the use of TO-92 appears to be able to circumvent problems encountered with sensitive SOT23 package for now. however when air temperature overshoots 45^oC, the 1uV dip/peaks resurfaces. in the TO92 variant, lowering of temperature removes the occurence, in SOT23, the noises persists longer. for TO92, the case temp is measured to be operating approx 10-12^oC lower than SOT23 (@200^oC/w, which suggests TJ = approx 70-80^oC)

there is also a hunch that the zeners (supposedly to regulate LTC1050 supply) are adding some noise? but i do not know for sure atm.

it appears that with better engineering/parts (in this case "tinkering") it could be likely to lower noise even further. if this buffer has a separate flatline DC supply, maybe the resolving power of the DMM could be improved even further?

[Kleinstein]

I asume the K2015 follows closely the K2000 schematics:

It's a little supprising to an effect from the small transistors. They are just two constant current supplys to provide the bootstrapped supply for the LTC1050. I would be more afraid of heat from the transistors heating up the OP - this is where the To92 case might be really better, as heat goes to air and not PCB. Still only a minimal difference expected.
A moderate size extra cap (e.g. 10µ Low ESR electrolytic) at the LTC1050 supply might give a minimal improvement, but don't expect much.

Much of the noise is likely just the noise from the LTC1050 itself and a little from the following stage. So not much improvements expected from the supply.

Though old the LTC1050 is still a good quality auto zero OP with low bias current. Its easy to find lower noise ones, but they usually have too much bias.

[3roomlab]

i tried to simulate the setup. injecting a 10mV AC as virtual trafo ripple. it seems approx 100uV of noise could still make it to the 1050. as the entire 1050 circuit then floats on also a negative constant current, it is likely the output is also a float relative to the noise (on -ve rail?). its alot of variables im not sure of, so ima just change bitsy pieces and log and observe.

on a side note, i wonder how did keithley get to have the SOT23 behave so well. did they resort to binning the 3904/3906? if so, at our end, what could we do to bin such common parts    . in scouring the pdfs, there are only so few low noise BJT to swap around n "play" this portion.

**note that for that last log, i still have a small fan inside moving the air "slowly"

[Kleinstein]

I don't see higher demands on the small (SOT23) transistors for the current sources. The ones that get hot are not critical at all (they just need to deliver power), and the ones that set the current don't get really hot. Also noise should not be critical, as the current sources work against the output of the coarse buffer OP - so the voltage is set by the OP, that just needs to drive the difference in currents (not critical) and the output current of the 1050. Even low qualitiy jelly been NPN/PNPs should give a resonable higher impedance current source.

I don't know how good the model for the LTC1050 is, but i don't think PSRR should be so poor at 100/120 Hz. I would not expect much noise/ripple at the OPs supply - just noise form the OP driving the supply and the noise from the zener diodes. Here keithly might have tested the OPs to find some with at least typical performance (low Bias).

The LTC1050 would be a candidate for an OP upgrade if you really want to get significant better - though this likely would mean using a lower noise type and selecting lower than typical bias (e.g. 1 out of 10). Modern OPs are not that much better than the LTC1050, but bias currents a parameter where binning might help.

[3roomlab]

  well, i dont think i have enough tech and knowledge on my hands to bin things properly at this stage. i read an interesting article about 1/f noise by Vojt?ch Janásek (http://www.janascard.cz/PDF/Design%20of%20ultra%20low%20noise%20amplifiers.pdf), it made me want to find out more about lower noise BJT to the extend to wanting to measure 1/f noise. maybe in this instance, ability to measure which node has most 1/f noise could help  . but that would mean making something with really low low noise. arrgh need more (low noise) gear to enable more (low noise) gear, chicken and egg problem lol

the interesting thing in his article is about parralleling BJT to achieve even lower noise. which is financially viable since parrallel LTC1050 opamp (or other low noise) would cost a crazy amount if in order to somewhat bin a stock of op amp or other BJT

some interesting update
2nd hr
AVE : -0.37uV
SKW : -0.126
KRT : 0.067
SDV : 0.214 (o no!)
ADV : 0.170
TRM : 0.995
( each hr, the SDV reduces about 0.01 -- 0.188, 0.174)

5th hr (trafo temp 43.5C) plot 0415
AVE : -0.61uV
SKW : 0.0002 (<--- nearly a straight line)
KRT : 0.0158
SDV : 0.1689 (new low!)
ADV : 0.1345
TRM : 1.0000

addon** 6th hr looking good too
AVE : -0.60uV
SKW : 0.043
KRT : 0.081
SDV : 0.1761
ADV : 0.139
TRM : 1.0007

i think i will keep this running to see how far will the stability last lol

[lukier]

Vojtech Janasek's papers are quite interesting. I want to build his variant of Wien bridge oscillator at some point (140 dB THD!).

Want to measure low noise? This might be helpful:

https://www.eevblog.com/forum/projects/low-frequency-very-low-level-dc-biased-noise-measurements/

and of course Jim Williams' classic, AN124 from Linear.

In general it is quite tricky. Expensive or preselected capacitors, plenty of shielding, careful power distribution (avoid ground loops, batteries), low noise JFETs and a lot of patience etc.

Once I wondered if I could measure noise with my lock-in amplifier, it has 6nV/sqrt(Hz) input noise and plenty of dynamic range. But then I would have to modulate the DC signal of interest with lock-in reference output (e.g. switching voltage reference on/off with a transistor) but then I suppose the switch circuitry would produce more noise then the DUT.

[3roomlab]

in the thread there is something very interesting about the eneloop plot post#65 by andreas. 0.1uV p-p noise only ! wow ? i wonder what if its LIFEPO4. and then power the DMM off this low noise DC pack.

update** now that ppl are starting to wake up ... burst noise is also appearing in the logs. but unlike previous logs, log 0615 still holds under 0.2 SDV.

[Kleinstein]

The amplifier needs to have low voltage noise, low current noise and a low bias. Usually low current noise also means now bias.
It's rather easy to find OPs that are better in either voltage or current noise, but difficult to get both in one amplifier. BJT OPs usually (eccept LT1012 or similar, which have too much voltage noise) have way to much current noise. As there is a 100 K resistor (or the impedance of the divider) or so at the input, a 1 pA noise current is equivalent to 100 nV of noise. So BJT OPs are practically not an option, despite of the low voltage noise. There can be additional current noise from leakage currents, even if they compensate - so a clean board is important.

Also because of drift, the input essentially needs to be a Auto Zero OP like the LTC1050. Though old this is still a good type for this purpose. Having two of the LTC1050 in parallel increases noise and bias current - so this may no be better overall.

If you really need low noise there may be no way around an amplifier that is adapted to the specific signal source. For low impedance sources one can use a an amplifier with low voltage noise, but higher current noise. This may not need so excotic components. This might also need an adapted overvoltage protection.  So usually an external amplifier is needed, close to the signal source. The DMM than only needs to have low noise in the 10 V range where it works best.

[3roomlab]

what is your opinon of ADA4638 powered @ 10v. the spec have some interesting numbers. it doesnt seem like a widely used opamp (maybe the 10Hz noise is terrible haha)

[Kleinstein]

The ADA4638 is a AZ OP und thus has essentially no 1/f noise.
The trouble is, that it has quite some bias current (40 pA typical) - thats a little high for a DMM input.
Noise is only slightly better than the LTC1050 (1.2 µVpp vs. 1.6 µVpp for 0.1-10 Hz).

The AD8638 would be similar in bias to the LTC1050 und lower noise (1.2 µV with 1.5 pA typical bias).

The rather comon AD8551 is also quite good (1 µVpp with 10 pA (typical) bias),
It's 5 V only , but this is not a big problem in the bootstrapped configuration.

Another low noise, but rather high bias option would be the AD8628, at 0.5 µVpp and 30 pA bias.

But keep in mind there are also other soures of noise, like the resistors itself and the following stage which should give something like 0.7µVpp of noise if based on OP177.

It should be resonable easy to check how much noise comes from the stages past the input buffer stage: current measurements start essentially from there. So one should compare the noise in voltage (e.g. 0.1 V range) with the current mode noise.

[3roomlab]

i guess if i cant cure my "itch", i might just opt to start trying opamp swaps lol

i recieved my package of BC550C/BC560C today and replaced all the NPN/PNP BJT. the plot is much quieter now, BUT A STRANGE ITCH TELLS ME, it is still not quiet enough  (after seeing robrenz 152hr log SDV of 0.076uV !!! on his tektronix 4050 !!! WOT ?? )

the front end of the plot is just coming out of a warm up, and same as before internally there is a small circulator fan.
AVE : -2.21uV (internal air temp 41.5^oC)
SKW : 0.035
KRT : -0.014
SDV : 0.166 (sample 500-3600)
ADV : 0.132 (sample 500-3600)
TRM : 1.001

it also appears, this is equivalent to 1 of the 2N39xx logs with partial TO92 mod
anybody have even lower noise BJT to recommend? 

[Kleinstein]

If the 166 nV Std. are for 10 NPLC setting  this is allready rather close to the nominal noise of the LTC1050. Noise Bandwith is 2.5 Hz and thus the 166nV Std means about 100 nV/Sqrt(Hz) of noise in case of white noise. This not much more than the 90 nV/Sqrt(Hz) specified for the LTC1050.

The plan also has other noise soures, like a 20 K  resistor that gives about 15 nV/Sqrt(Hz) and the OPA177 in the gain stage which might give a similar noise contribution.

It's no suprise to see not much difference between the diffrent transistors in the current sources - the 2 ones that get hot not even have much influence on the current. Noise from the current sources should be hardly detectable at the output. It's more likely a thermal effect that is possible from the small SOT23 transistors. 

[3roomlab]

i see, i dont quite understand the calculation, how does 1 do the conversion from PDF spec nV/sqrt(Hz) to compare the SDV? if 10NPLC approximates to 100nV/sqrt(hz), how do we translate robrenz's tek4050 (73nV SDV)? i think i caught a glimpse of his SDV in the LTZ1000 or was it the LM399 discussion thread. found it (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153), is the lower noise record due to 100NPLC?

since a few hours have gone by, there is some logs in the bag. originally the intent of the mini fan inside was to circulate air and reduce some temperature, but now as i have converted fully to TO-92 BJT, i thought i log some w/o fan working. and it came out even better. no pops and sizzles ! yum yum !

i will just copy the XLS result as is, the numbers are arranged as follows
AVERAGE | | STDEV (in nV) all plots are 100mV scale 10NPLC, AZERO on. manual REL +2uV
SKEW | | AVEDEV
KURT | | TRIMMEAN

plot 0204
-324.7052777778   526.0146096479
-0.1100208528   525.8307811728
-0.799885848   1.0006576714

plot 0304
-1470.1225   157.6810638436
0.1302137461   125.8797902778
0.178574312   1.0009115936

plot 0404
-1402.9163888889   179.471967593
0.1201923798   158.0596367284
-0.2535748744   1.0012086594

plot 0504
-1141.2641666667   153.2140025044
0.005902222   123.2643449074
0.2425810864   1.0002417992

plot 0604
-1085.2594444445   153.3506986219
0.0867791975   122.6290722222
-0.0720036643   1.0008171796

plot 0704
-1128.9155555556   155.5941890996
0.0283555016   123.0794123457
-0.0130345579   1.0000723408

*edit : i should also add that the FLIR-ed temperature of the BC5xx BJT is approx 41^oC. that is way way under the 61-65^oC of the SOT23 BJT packages. i also need to mention that the bootstrapped current regulator resistor has been modded also to a higher value of 172ohms from 150ohms, a reduction of approx 0.5mA

final PCB air temperature 43.2^oC, trafo temp 42.8^oC
hmmm another 50nV to shave off perhaps  ... well this is getting exciting 
(come to think of it, all along i had the wrong impression that the noise came from my dirty AC mains, and i have not added the large 100mH filter yet)

[lukier]

i see, i dont quite understand the calculation, how does 1 do the conversion from PDF spec nV/sqrt(Hz) to compare the SDV? if 10NPLC approximates to 100nV/sqrt(hz), how do we translate robrenz's tek4050 (73nV SDV)? i think i caught a glimpse of his SDV in the LTZ1000 or was it the LM399 discussion thread. found it (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153), is the lower noise record due to 100NPLC?

It is probably due to 100 NPLC. Today I was playing a bit with my 3457A and after a long warm up, on the 30 mV range, with 10 measurements (NPLC 100, NRDGS 10, single trigger, MATH STAT) I got around 40-50 nV std. dev. With 10 NPLC ~120, with 1 NPLC 400-500 AFAIR.

However this was only 10 samples = 20 s. I doubt I could get Robrenz's 73 nV over 152 hours. Not even due to the multimeter itself, but my lab has uncontrolled temperature and way too much switchmode gear always on, therefore RF interference unstable mains I suppose.

[3roomlab]

hmmm 100NPLC, @lukier do you have plans to put a AC isolation transformer to counter some AC noise? or maybe common mode filter etc?

my DMM is running next to a bunch of PCs, so i think there is still noisy AC here

[lukier]

hmmm 100NPLC, @lukier do you have plans to put a AC isolation transformer to counter some AC noise? or maybe common mode filter etc?

Not anytime soon. It is hard to find nice shielded medical grade ones on ebay (in the EU at least, and these things are heavy) and I'm not sure about the builders variety (called site transformer), a lot of them have 110V secondary, don't know why, seems useless in the EU.

Should get one at some point, or a HV differential probe, because recently I almost fried my DS1054Z by careless probing around SMPS. Fortunately RCD + fuse switched the power off quickly and even the probe survived.

[3roomlab]

If the 166 nV Std. are for 10 NPLC setting  this is allready rather close to the nominal noise of the LTC1050. Noise Bandwith is 2.5 Hz and thus the 166nV Std means about 100 nV/Sqrt(Hz) of noise in case of white noise. This not much more than the 90 nV/Sqrt(Hz) specified for the LTC1050.

The plan also has other noise soures, like a 20 K  resistor that gives about 15 nV/Sqrt(Hz) and the OPA177 in the gain stage which might give a similar noise contribution.

It's no suprise to see not much difference between the diffrent transistors in the current sources - the 2 ones that get hot not even have much influence on the current. Noise from the current sources should be hardly detectable at the output. It's more likely a thermal effect that is possible from the small SOT23 transistors.

noob question. how do i derive 100nV noise from 2.5Hz bandwidth and how do i know it has to be 2.5Hz? 10NPLC in my mind seems like "averaging" of 10 power cycles, is this how all NPLCs work in general? like a form of averaging?

to add on some more plots to verify under 160nV plots, i guess this is really the practical limits of the currrent mods (capacitors + TO92 BJT)
plot 2030 : SDV 153nV (0.1v scale 10 NPLC, REL : manual, 3600 samples, 1 sample/sec)
plot 2130 : SDV 156nV
this run is taken without circulator fan (running air temp 44^oC), there was a previous test run with circulator fan running on the raw 7v rail, it produced about 3nV extra noise (strangely low, notable but seems beyond reliable resolving power of the DMM, but wait should it be considered?), running air temp was approx 41^oC. this run is done setting up in another room w/o any electrical appliances, but it seems no different from being logged in the "noisy" room (same AC power phase in any case). i do suspect there is some amount of thermal EMF noise in it, but i have no idea how to verify that component (or more importantly, to remove it !  pls feel free to give me ideas to try )

[lukier]

noob question. how do i derive 100nV noise from 2.5Hz bandwidth and how do i know it has to be 2.5Hz? 10NPLC in my mind seems like "averaging" of 10 power cycles, is this how all NPLCs work in general? like a form of averaging?

I too think that higher NPLC is sort of equivalent to averaging, but I stand to be corrected what is exact difference. I suppose higher CMRR with higher NPLC and the averaging there happens in the integrator of the multi-slope converter, thus slightly before being converted to the digital form. Averaging ADC readings might produce slightly different results due to limited numerical precision and quantization I suppose. Also this NPLC business assumes Gaussian nature of the noise if I'm not mistaken.

Keithley 2001 and 2002 have synchronous autozero, so I suppose it senses AC mains with zero crossing to synchronize ADC operation in a precise manner.

[Kleinstein]

I agree with lukier on how the NPLC / averaging works. Depending on the DMM, higher NPLC settings may actually use averaging.
So it is expected to see the noise (e.g. STD value) go down with about the square root of the number of PLC. At very slow measurements drift and 1/f noise can make the noise higher than expected. But at least the noise from the LTC1050 has essentially no 1/f noise.

At 10 NPLC the signal is integrated of 10 cycles or 1/5 s. This gives an effective Bandwidth of 2,5 Hz - assuming white noise and no extra filtering.

Using an integer number of power line cycles gives a very good suppresion the power line coupling. So there measurements are hardly sensitive to coupling from the transformer or similar. Things can get very different for the faster than one power cycle - these measurements might resolve the coupled signal and thus can give much higher RMS values.

For AC suppresion the timing does not need to be really syncronized to zero crossing - coupling can produce phase shifts and thus it is not clear how the phase of the signal coupled to the input is.

The best way to get really low noise, is to use a seprarate external amplifier and use the DMM in the 10 V range. There are AZ OPs available at 1/15 the noise of the LTC1050, but these have to much bias to be used as an universal amplifier in a DMM. Also the protection circuit might produce more noise.

[3roomlab]

i was trying out combinations of NPLC + averaging to emulate NPLC 100. it seems i may have hit a good spot. it comes close to robrenz 0.073 uV, big big assumption here of using his SDV as a guideline for 100NPLC, and assuming this "moving averages" behaves similarly to NPLC method of reducing "noise" (or extending NPLC "range")

i think i finally understand how to use NPLC + MOV combination to extent the K2015 physical measurement limits. NPLC + MOV measurement bandwidth has to coincide with FETCH sampling rate (or at least sampling rate has to be slower). over-lapping of each sample will result in weird plots.

using NPLC10 + MOV6.@1.1Hz gives 90nV (SDV) <-- weird plot 0214
using NPLC10 + MOV5 @1Hz gives 79.20nV (SDV) plot 0505 <-- equiv of NPLC 50?
using NPLC10 + MOV4 @1.25Hz gives 92.05nV (SDV) plot 0838 <-- equiv of NPLC 40?
using NPLC10 + MOV6 @0.83Hz gives 73.67 nV (SDV) <-- equiv of NPLC 60?
using NPLC10 + MOV10 @0.5Hz gives 58.86nV (SDV) <-- equiv of NPLC 100?

REP averaging appears to be a totally different beast than MOV averaging. and the timebase is totally different. i think REP averaging is the correct method to extend NPLC as it takes averaging from X number of samples w/o regard for previous averaged value. however, it seems the limited processing inside K2015 requires about 3.3x more total sampling time.

1) using NPLC10 + REP5 @0.3Hz gives SDV 84.61nV <-- NPLC 50?
2) using NPLC10 + REP10 @6.6sec/sample gives SDV 63.15nV <-- NPLC 100? (136 samples)
3) using NPLC10 + REP10 @6.6sec/sample gives SDV 61.08nV <-- NPLC 100? (another 136 samples)
i am guessing NPLC10+REP100 will take 66seconds to process 1 sample  giving NPLC 1000 ! this is the reason why scientists need chinese elixir of long life, not enough time to collect samples !

mathematically speaking, if 6 averages of NPLC10 is equivalent of NPLC60, it would mean 100 averages would make the K2015 capable of NPLC 1000?

i think i am somewhat convinced that NPLC 1000 is quite possible and it could collect valid NPLC 1000 data. is my conclusion logical?